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ADC12J4000 SYSREF output of EVM

masahiko shimizu
Guru 11235 points
Other Parts Discussed in Thread: ADC12J4000EVM, LMK04828, ADC12J4000, TRF3765

Hi

My customer is using ADC12JxxxxEVM and TSW14J56 at ADC12J4000EVM GUI A Beta 2.1.
He set GUI as the attached file.
But SYSREF wasn't outputed from LMK04828 to ADC12J4000.
Could you advice me, please?

Best regards
Shimizu

ADC12JXXXXEVM_GUIsetting.xlsx

  • 0
    TI__Mastermind 44680 points

    Hi Shimizu

    In the default configuration of the ADC12J4000EVM the SYSREF output to the ADC12J4000 device is turned off. Having SYSREF continuously active causes noise coupling into the ADC and additional spurs in the captured spectrum. We recommend that the ADC SYSREF is only active when needed to re-align the device LMFC in a multi-converter application. The ADC will self generate the internal LMFC timing without an applied SYSREF so the default configuration works fine.

    Is there a reason the customer wants to operate the EVM with the ADC SYSREF active? Are they trying to verify multi-converter synchronization, or deterministic latency behavior?

    The ADC12J4000 and LMK04828 configuration files can be modified to enable the ADC SYSREF if needed. If that is required, please let me know which ADC mode (Fs, Decimation and Serial Data Mode) are being used and I will provide the needed files.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Guru 11235 points

    Hi Jim

    Thank you for your support.
    Customer is trying to verify multi-converter synchronization.

    Could you give me the needed files, please?

    Customer condition is following.
    Fs=3.2GHz

     Is there other necessary information?

    Thanks

    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Mastermind 44680 points

    Hi Shimizu

    If the customer is trying to test multi-converter synchronization with 2 ADC12J400EVM+TSW14J56EVM setups they will need to do more than just enabling the SYSREF outputs for the ADCs.

    They will also need to synchronize the SYSREF and DEVCLK signals between the two boards. That is possible, but will require some additional setup and board configuration changes. Please direct them to this TI Design which discusses this topic in detail.  http://www.ti.com/tool/TIDA-00467

    Best regards,

    Jim B

     

  • 0 in reply to Jim Brinkhurst1
    Guru 11235 points
    Hi Jim

    Thank you for your support.
    I add a question.
    Because customer would like to try only one board at using TRF3765 as first development.
    Customer would like to supply clock (DEV and SYSREF) from TRF3765 to ADC via LMK04828.
    Is it possible?
    If it is possible, Could you let me know how to change board setting, please?

    Thanks
    Shimizu
  • 0 in reply to masahiko shimizu
    TI__Mastermind 44680 points

    Hi Shimizu

    The clocking on the ADC12J4000EVM can be configured a number of different ways. It is possible to use the TRF3765 as the frequency synthesizer and use an output of the LMK04828 to drive the ADC DEVCLK input. Due to the divide-by-2 between the TRF3765 output and the LMK04828 input, the maximum possible DEVCLK frequency will be 4.8 GHz / 2 = 2.4 GHz.

    To enable this mode, the following hardware changes need to be made to the board (Refer to the schematics and assembly drawings in the ADC12J4000EVM design package http://www.ti.com/lit/zip/slac649):

    Remove C32 and C33. (Disconnect TRF_OutB+ and TRF_OutB- from DEVCLKP/N inputs)

    Install C262 and C263. (Connect ADC_DEVCLK+ and ADC_DEVCLK- to DEVCLKP/N inputs)

    In addition to the hardware changes, alternate TRF3765 and LMK04828 configuration files will be needed. Please let me know what TRF3765 frequency (this will be 2x the ADC sample rate) and decimation/serial data mode are desired. Once I have this information I can provide the modified files.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Guru 11235 points

    Hi Jim,

    Thank you for your support.

    I understood.

    Again, I request the following.

    Customer is using ADC12JxxxxEVM.

    Fs(Devclock)=3.2GHz.

     TRF3765 outputs 3.2GHz which is supplied to ADC12J4000 directly as device clock.

     LMH04828 outputs SYSREF clock which is set by GUI to ADC12J4000.

     LMH04828 is inputed 3.2GHz clock from TRF3765. 

     Condition is the below.

    Could you inform me the hardware changes and  give me modified file, please?  

    Is there other necessary information?

    I think SYSREF clock can change on GUI. Is it correct?

    Thanks

    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Mastermind 44680 points

    Hi Shimizu

    The hardware will not need to be modified for that configuration.

    The only changes required are to update the ADC12J4000 configuration to enable the SYSREF receiver and processing, and the LMK04828 configuration to enable the ADC SYSREF output. The two files attached below have the necessary changes.

    LMK04828_DB1_Fs_3500Msps EN ADC SYSREF.cfg

    ADC12J4000_DB1_DDR_EN_SYSREF.cfg

    Copy these files to the following folder location: C:\Program Files (x86)\Texas Instruments\ADC12J4000EVM GUI A\Configuration Files

    These files can be used two different ways. The ADC can be configured normally for 3200 MSPS onboard clocking, with DDC Bypass mode and then these updated files can be loaded one at a time using the Load Config button on the Low Level View tab. 

    The other option is to use these files in place of the ones that normally get loaded. To do this first rename the original files, adding a .bak suffix.

    ADC12J4000_DB1_DDR.cfg becomes ADC12J4000_DB1_DDR.cfg.bak

    LMK04828_DB1_Fs_3500Msps.cfg becomes LMK04828_DB1_Fs_3500Msps.cfg.bak

    Then rename the new files to the following:

    ADC12J4000_DB1_DDR_EN_SYSREF.cfg becomes ADC12J4000_DB1_DDR.cfg

    LMK04828_DB1_Fs_3500Msps EN ADC SYSREF.cfg becomes LMK04828_DB1_Fs_3500Msps.cfg


    Now when the board is configured for 3200 MSPS onboard clocking in DDC Bypass mode, these new files will automatically get loaded.

    With the new files, the ADC SYSREF is continuously active.

    Best regards,

    Jim B