Hello,
We are designing device with two daisy-chained ADS1278, connected to MX51 application processor in SPI, TDM fixed mode, CLK and SCLK connected together and operating at 3.2MHz.
It’s not clear for me how the SYNC signal should be used.
From the documentation and this forum I have learned that the SYNC signal should be pulsed after at least one DRDY pulse (SYNC immediately after power on is not enough).
But I’m not sure if in SPI mode, the SYNC signal need to be pulsed again after CLK was interrupted? I’m not sure if the sentence in documentation "If the clock inputs (CLK, FSYNC or SCLK) are subsequently interrupted or reset, re-assert the SYNC pin" apply only to FrameSync mode or to both SPI and FrameSync modes? I'm also not sure what is considered as clock interruption?
It’s important to me, because I’m considering to sync the ADS1278 by
- In initialization stage clocking them “manually” (setting SPI interface to GPIO mode and applying CLK programmatically at low speed), then asserting SYNC signal after DRDY
- And later in data acquisition stage, reconfigure SPI interface to SPI with DMA. But this reconfiguration would cause interruption (not sure what is considered as interruption) in CLK signal.
If CLK could not be interrupted without need to re-assert SYNC signal, then possibly I have to add some additional hardware (like latch controlled from CLK and some GPIO from CPU) to drive the SYNC signal while operating SPI in it’s “normal” configuration (SPI with DMA). Without the additional hardware (latch), I could set-up interrupt from DRDY and pulse the SYNC from the interrupt, but I afraid that it would not run reliable enough to meet the timing requirements between the CLK and SYNC signals (the MX51 is running Windows CE OS).
Regards
Dariusz Czarnecki
