ADS1292 - Changing resolution and speed complications

ricardo marinheiro

Other Parts Discussed in Thread: ADS1292, ADS1292R

Hi.

We are trying to use an ADS1292 for vital signals aquisition.
At the moment there are a few problems we are facing without explanation or solutiuon, hence, I'm asking for some guidance here today.

1st: We have very good signal reading from the ADS from 125sps until 500, as soon as we select 1ksps, the signal arrives full of spikes. These happen +/- every 500ms. If we select 2Ksps then 250ms... etc
The code that makes the reading by the nREADY interrupt is the same for all the tries. Bellow 1Ksps works fine, above is spiky and noisy. The reading system could go up to 20ksps if needed.

2nd: Once our system is prepared for a 12bit sampling, we where hoping that a simple passage from 24 bits to 12 would be enough for signal reconditioning.
We observed that the signal was in fact falling on the right averages but a lot smaller, leading to the question, why isn't the signal being read at 24bit with the same magnitude when compared to a 12bit ADC, injected with the same source.

he config2 voltage is being left with the default of 2.42v ref.
2 leads only, there is no RLD setup. Design circuit is according to Figure 56, of page 58.
Avdd is 2.5V

Thank you very much for time and attention to our complications.
And thank you in advance for your reply and help.

-- Ricardo --

over 10 years ago

0 Brian Pisani over 10 years ago

TI__Mastermind 38745 points

Hey Ricardo,

First, when you say that AVDD is 2.5 V, is AVSS at -2.5 V? This device requires that (AVDD - AVSS) be at least 2.7 V. Assuming the power supplies are within the correct range, I will suggest solutions to each of your problems below:

1. I have seen very similar problems in the past where the bit rate of the master is ostensibly fast enough to collect all the data for each sample, but delays that are introduced incrementally on each sample due to some other process that the mircrocontroller is busy with. These delays accumulate and eventually lead to a distortion in the data when a DRDY pulse occurs in the middle of an ongoing SPI transaction. What is your microcontroller doing when it is not collecting data over the SPI? Does that operation tend to use a significant amount of bus bandwidth (i.e. USB streaming, moving chunks of data around in memory, nested function calls)? I highly recommend you check for this by checking the timing of a few data collections on the oscilloscope. Check what the timing is at "random" times to see if the time it takes from DRDY falling low to the first SCLK rising edge varies significantly at the higher data rate.

2. I'm not quite sure what you mean when you say the signal has "the right averages" but is "a lot smaller". Does that mean that for a given DC input there is a different DC output from one device to the next? Are you certain that your method of converting the output bitstream from the ADS1292 is parsing out the channels correctly and bit-shifting them by the correct amount?

Regards,
Brian Pisani

0 ricardo marinheiro over 10 years ago in reply to Brian Pisani

Prodigy 70 points

Hi Brian, first of all, thank you for such a fast reply!
The supply is correct, as we are giving it 3v from a battery.
As to the sampling rate, I've tried 2 methods, both with same outcome.
Interrupt based reading with about 50us delay from nReady pull, before start reading data from chip.
The second option was a constant poll on the device by monitoring the ready line, again with a small 50us delay before reading.
Both work fine till the 1ksps While the system is reading, the interrupts are disabled and enabled on the exit.
I tried something else that is less orthodox but usually gives some hints over RC based clocks... I've varied the analog input between 2.7 and 3.6, the artifacts were more noticiable at 2.7 and 3.6 and almost disappeared at 2.95V.
I've also implemented several over reading and under reading testes just to understand behaviours...
So my question would be, may I just keep running the ADS at 1ksps for example and just read 10 times a second? Is it mandatory to read every time the ADS gives a ready signal? Does it accumulates values or do they overwrite in anyway? Am I allowed to read the registers at any time I want even in between samples? does the ADS complain if I read with the ready set?

Thank you once again Brian

0 Brian Pisani over 10 years ago in reply to ricardo marinheiro

TI__Mastermind 38745 points

Hey Ricardo,

Input needs to remain within the analog supply range. An input of 3.6 V is outside of the valid conversion range for the device. In addition, the reference only goes up to 2.4 V, so really that is the largest positive differential voltage you will be allowed to measure. At any rate, you are likely exceeding the absolute input range as well as the differential range. Information regarding the valid analog input range for the device can be found in the datasheet.

You must synchronize collections to DRDY. Tolerances on oscillators will make it impossible to use the microprocessor's clock to time collections reliably. The device does not accumulate samples in a FIFO. Each sample must be read between DRDY signals or the sample will be lost. Complete information regarding the interface and the format of data can be found in detail in the device's datasheet.

Regards,
Brian Pisani

0 ricardo marinheiro over 9 years ago in reply to Brian Pisani

Prodigy 70 points

Hi Brian, once again,

Thanks, that acctually helped a lot, once we where using correct supply, bad incorrect referencing.
Also, to convertthe signal to the needed 16 bit we have use a movable window of 16 bit inside the 24bit in roder to select the correct signal, meaning that every time we divide by 2 we use another msb bit. Works just fine

Eventually we incurred in another problem, that if you think would be usefull to, we might just open another support title, about the spi interface.
At first for proff of concep, we used regular poll on SPI TX END on our controller in order to wait to send a new byte. This created a window of apporx 4us space in between bytes.
Everything worked fine. At the moment we're properly organizing the code for the libraries, at which point we've changed it to use DMA transfers.
The ADS stopped working. I've mapped the whole communication on a logical bus analizer, and reallized that the only differences from the previous implementation were 2:
- The DMA will once in a while expand certain bits and respective clock edge while the uC is attenting to other interrupts. Nothing new, allways seen this almost everywhere, hence the clock edge to read data.
- We've seen that the DMA does not delay in between bytes, just clocks everything out in a row.

My question is, is it know that any of these observations would create an erroneous work on the ADS1292R side?
Is ther any time spec in between bytes that is mandatory to take in consideration that a continous stream of clocks does not respect?
Is it mandatory to always have delay in bewteen bytes in or out?

I've tryed to understand it from the datasheet, but is ambiguous the explanation once the only drawing shows merely 1byte out and 1byte in exchange.

Thank you once again for the help

0 Brian Pisani over 9 years ago in reply to ricardo marinheiro

TI__Mastermind 38745 points

Hey Ricardo,

None of those sound like they are causing the issue, but one issue that I have heard other users encounter is when there is a gap in between chunks of toggling SCLKs, the microcontroller may bring CS high resetting the slave's interface. For me to help you understand further, take a screenshot of the interface on a logic analyzer of oscilloscope. The most helpful signals would be DRDY, SCLK, CS, and DOUT (MISO). DIN (MOSI) is not necessary because when you collect data, I imagine you are sending 0x00s to the slave.

Regards,
Brian Pisani

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ADS1292 - Changing resolution and speed complications