• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 281 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CMOS output mode of ADS62P29EVM

Lingmei Ma
Intellectual 330 points
Other Parts Discussed in Thread: FMC-ADC-ADAPTER

Hi, I have some problems with using ADS62P20EVM in CMOS mode, and I was wondering if anyone can provide some suggestions.

I configured the ADC to work at CMOS mode by setting JP14. The input clock is in burst mode- multiple cycles of 100MHz square wave with  VH=1.5V and VL = 0V.

the outputs of ADC are routed to a FPGA evaluation board (Xilinx ML605) by TI's FMC-ADC-ADAPTER. IOSTANDARD of the FPGA is configured to be LVCMOS. Vcc of the bank is 2.5V.  According to the datasheet, VIH is 65% of Vcc, so 1.8V output voltage should be enough.

But when FPGA board is connected, the output clock of the ADC becomes strange. In the figure below, the white line is the output clock of ADC without FPGA board, and the green line is with FPGA board. It seems there is impedance mismatch, which I do not understand. Can anyone point out what I have done wrong? Thanks.

Lingmei

  • 0
    TI__Guru* 91947 points

    Lingmei,

    How are CTRL1,2,3, SCLK and RESET configured on your EVM? Are you issuing a reset as described below after power up?

    Register Initialization After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as shown in Figure 9 OR 2. By applying software reset. Using the serial interface, set the bit (D7 in register 0x00) to HIGH. This initializes internal registers to their default values and then self-resets the bit to low. In this case the RESET pin is kept low. 

    What position is the shunt in on JP14?

    Are you setting the part into low speed mode by any chance? This will only allow the part to work at a max sample rate of 80MHz.

    Have you tried using a continuous clock to see if this improves the clock output? Have you tried a slower sampling rate to see if your test equipment is having an issue with this measurement? 

    Regards,

    Jim