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DAC3484 layout rules and trace lengths for FRAME, Sync, and DATACLK

PeterH
Prodigy 125 points
Other Parts Discussed in Thread: DAC3484

Hello,

I'm using a DAC3484 on my pcb which has the data, frame, sync, and DATACLK pins driven by an fpga.

Looking at the layout I can see the following trace lengths:

frame dp/dn = 839.6 mils  / 832.8 mils

sync dp/dn = 1334.5 mils / 1232.98 mils

DATACLK dp/dn = 1133 mils / 1140.7 mils

DACCLK dp/dn = 925 mils/ 1000 mils and driven by an LMK0482BISQ

For the DAC data pins I'm seeing diff pairs that range from 349 mils for one pair to 845 mils for another pair.  Each diff pair is reasonably length matched between the dp and dn.

I'm running the DAC in word-wide format.  The DATACLK = 122.88 MHz with a 90 deg phase shift to align the edge of the DATACLK to the middle of the 16-bit dataword.  

I'm only using IOUTA and IOUTC ch B and D are unconnected.

Can you tell answer a few questions for me:

1) Are DATACLK, sync, and Frame supposed to be length matched? 

2) Are the lengths above ok to get the data to appear at the chA and chC output of the DAC3484?

3) What kind of tolerance in lengths are acceptable if the frame, sync, and dataclk lengths are as we have them?  Are they supposed to be within 100mils or 200mils or xyz mils of each other?

For the DAC3484 chip do you have any recommended appnotes that I can refer to for interfacing it with an fpga?

Thank you very much for your help,

Peter

  • 0
    TI__Guru* 97425 points
    Peter,


    I'm sorry I didn't notice this post earlier, but this is an HSP part and this post belongs in the High Speed Data Converters Forum.

    I've moved this post and hopefully one of the engineers that covers this forum can help you out.


    Joseph Wu
  • 0
    TI__Guru* 78124 points
    Peter,

    Regarding the differential pair positive to negative matching, you might be OK with framep/n and syncp/n since these are meant to be low frequency control signals (i.e. < 100MHz). For the DATACLK and DACCLK that could potentially go beyond 500MHz to 1.25GHz, you may need to perform an IBIS model simulation to see if there are any impact on signal integrity and timing. The DAC3484 IBIS model is available on the DAC3484 product folder page.

    On our EVMs, we have all the differential pairs positive to negative matched to less than 5mil difference. The reason is that we have to ensure good operation over the entire possible evaluation scenario.

    Regarding your DAC data pins, you are seeing differences among the pairs as much as 500mils. Assuming rule of thumb for FR4 material of 120ps/inch of prop delay, you may see about 60ps of prop delay difference among the pairs. This will reduce your overall system timing margin. You might be able to get away with this since your effective data toggle rate is 122.88MSPS, or about 4ns bit period. You may still have sufficient data valid window left. However, this is highly depended on your FPGA driver and the overall routing of your PCB.

    On our EVM layout we have pair to pair matching of 10mils max.

    Refer to the DAC3484 datasheet page 14 for the setup/hold time requirement, you may find that the minimum data valid window is Ts + Th = 500ps. The setup/hold can be adjusted either to clock delay or data delay. With the DAC's valid window requirement of 500ps and your effective data window of ~4ns, you have about 3.5ns left for budget from FPGA and PCB trace. If you can make sure that your overall valid window can still meet the DAC's requirement, this should be OK. I highly recommend you perform IBIS simulation as well as scope measurements of eye diagrams to double check.

    Overall, your PCB layout may be OK to get the data out, but you will need to make sure other factors such as FPGA timing budget and temperature variation will not impact your data valid window.

    Take a look at the follow app note for some guidance on FPGA/DAC interface:
    www.ti.com/.../slaa545.pdf

    -Kang