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ADC12J400 huge SFDR degradation in a small zone of the spectrum

Manuel De Matos
Prodigy 30 points
Other Parts Discussed in Thread: ADC12J4000, ADC12J4000EVM

Hi all,

we are using the ADC12J4000 on one of our board (4 ADCs). It behaves globally as expected, except in a small part of the spectrum where the SFDR loose about 10dB.

Did anybody see such behaviours?

I did test with the following sampling frequencies : 3.0, 3.2, 3.4, 3.6, 3.8 and 4.0GHz.

Depending on the sampling frequency, SFDR degradations happens when the carrier is between 80MHZ an 100MHz from Fsampling/2. There are 2 spurious on each side of the carrier which appear when the carrier is in this part of the spectrum.

If I lower the carrier power, then these spurious disappear suddenly when the level goes below between  -3.5dBFs and -4dBFs (depending on the ADC).

Moreover, the zone location seems to be proportional to the sampling frequency.

To do the SFDR measurements I removed from the spectrum the signal's harmonics and the interleaving offset spur at Fs/4.

The ADC configuration is as follow:

- enable large signal

- foreground calibration

- disabled background calibration

- enable timing calibration

- carrier level about -1dBFs

regards,

Manuel

  • 0
    TI__Mastermind 44680 points

    Hi Manuel

    I've done some measurements using the ADC12J4000EVM, and so far I have not been able to reproduce this behavior that you are seeing.

    Can you provide a few FFT plots with the full Nyquist zone, and zoomed in showing the spurs, and the detailed Fs and Fin conditions used?

    Thanks,

    Jim B 

  • 0 in reply to Jim Brinkhurst1
    Prodigy 30 points

    Hi,

    thank you for your reply. For the attached screenshot, I used :

    - Fs : 4GHz

    - Fin : 2 100 006 103.52Hz, because I use a 2.05-2.150 GHz pass band filter to remove the signal harmonics.

    - FFT length : 8192 samples



    Problem at 1-dBFs

    Zoom on the problem zone

    problem at -3.5dBFs zoomed

    problem disappeared at -3.6dBFs

    Thank for looking at this issue.

    regards,

    Manuel

  • 0 in reply to Manuel De Matos
    TI__Mastermind 44680 points

    Hi Manuel

    I haven't been able to replicate those spurs at 100 MHz offset in the default EVM configuration. I was able to see a small spur at 1800 MHz when I disabled the JESD204B link scrambling feature.

    Is the link scrambling feature enabled in your design? Scrambling is included to reduce any effects of repeating pattern data causing coupling to other elements in the system, etc. If this is not enabled that might be the cause of the spurs you see at large signal levels and particular frequencies. If scrambling is enabled then the data link is likely not that cause of the problem.

    Another potential coupling path would be from the ADC power supplies into the analog input path, or clock path. These are also potential paths for unwanted noise to affect the converter performance.

    Best regards,

    Jim B

     

  • 0 in reply to Jim Brinkhurst1
    Prodigy 30 points
    Hi Jim,
    thank you for your suggestion.
    Unfortunately, the scrambling is enabled, nevertheless, I will check carefully the JESD configuration.
    Indeed, according to the tests I have done, the frequency of the spurious seems to be linked to the sampling frequency.

    regards,
    Manuel