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AFE7225 Clocking

JB63
Prodigy 230 points
Other Parts Discussed in Thread: AFE7225

Will be clocking the AFE7225 using a single-ended LVTTL 60 MHz clock and enabling the single-ended buffers for DAC and ADC on chip.

Will connect coupling caps to pins 8 and 9 and then tie together (per data sheet) and feed from a single LVTTL clock.

Question: What is the acceptable level range when using the single-ended clock inputs?  Can we drive them directly with LVTTL (3.3V) levels?

Thanks,

John

  • 0
    TI__Genius 9695 points

    Hi JB63,

    The typical clock input level is 1.5Vpp for the AFE7225 though higher is good. The part is also expected to work with input level as low as 200mVpp.

    It is ok to drive with LVTTL if you ac couple so as not to disturb the common mode of AFE7225.

    Thanks,

    Eben.