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Can DAC38J84EVM working at 2211.84MSPS with onboard PLL

user1405755
Prodigy 90 points
Other Parts Discussed in Thread: DAC38J84EVM, LMK04828, LMK04821, DAC38J84

Hi there,

I am working on DAC38J84EVM board, I've already realize 552.96MSPS data input rate and 2211.84MSPS output rate with External clock, but this seems complex if a demo system using more than 10 such board (cause using too many dividers and cables). Thus can someone help me out how to configure inner VCO/PLLs and on board LMK04828 to reach required data rate, SYSRef and JESD clock?

  • 0
    TI__Guru* 78174 points

    Hello,

    The LMK04828 family (LMK04821, 04826, and 04828) does not support the VCO frequency of 2211.84, so you will need to use the DAC38J84's on-chip PLL to generate the 2211.84MHz DAC sampling clock and also take reference from the LMK04828 clock in order to avoid using an external reference source.

    I would suggest doing the following:

    1. Use your existing, working DAC38J84 EVM configuration at 2211.84MHz external clock mode, configure the DAC38J84's on-chip PLL only to generate the internal DAC38J84 on-chip 2211.84MHz DAC sample clock.

    1.a. divide the external 2211.84MHz clock source on LMK04828 CLKOUT2 to a PFD range acceptable to the DAC38J84's on-chip PLL range. The typical PFD frequency of the DAC38j84 is less than 500MHz. The divider setting of CLK2 can be found on the LMK04828 page of the software.

    1.b. use the DAC38j84's on-chip PLL N and M divider and on-chip VCO range to generate the on-chip 2211.84MHz clock.

    2. Once you have the DAC38j84's on-chip PLL configured, you can try to generate the needed reference clock for the DAC38J84's on-chip PLL. You may configure the on-board LMK04828 in PLL2 mode with the desired CLKOUT2 frequency needed for the setup 1 to work.

    Please refer to the DAC38J84 on-chip PLL section of the datasheet and the LMK04828 datasheet for configuration detail.

    -Kang