Hi,
I would to confirm the operation of the MUX.
When MUX[3:0] is set "1100:(AVDD – AVSS) / 4 monitor" , where is the AINN of PGA connected ?
Thanks,
Kuramochi
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Hi,
I would to confirm the operation of the MUX.
When MUX[3:0] is set "1100:(AVDD – AVSS) / 4 monitor" , where is the AINN of PGA connected ?
Thanks,
Kuramochi
Hi Kuramochi-san,
As stated in the ADS1120 datasheet on page 29 in section 8.3.11, when using the system monitor the gain is set to 1 and the PGA is bypassed. Internally there is a voltage divider, but unfortunately I cannot give further details about the voltage divider nor how the voltage divider connects to the inputs. However, in this case AINN is bypassed from the PGA, so the PGA common-mode restrictions do not apply when the system monitor is being used.
Best regards,
Bob B
Hi Kuramochi-san,
The internal reference is used when measuring the external reference. The full-scale range is +/-2.048V at a gain of one. The LSB size is the full-scale range divided by the total number of codes resulting in 62.5uV per code. If we divide the reference by 4, the input to the ADC is 1.05V. To get the total number of codes, we divide 1.05V by the LSB size and get 16800 codes, or about 0x41A0. The actual returned value will be approximately VREF/4. The value 0x2000 is about 512mV, which would be the value of the internal reference. To measure the external reference you need to select the desired reference by setting the appropriate VREF bits in the Configuration Register 2.
Best regards,
Bob B
Hi Kuramochi-san,
The voltage divider is required for measuring a voltage that is greater than the internal reference. For example, if AVDD is 5V and the internal reference is 2.048V, then I must have a divide by 4 to be able to measure the voltage. A divide by 2 in this case would still give me full scale, so divide by 4 is required.
Best regards,
Bob B