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ADS5294 sync feature

Suhas Raja Chandragupta55
Intellectual 1690 points
Other Parts Discussed in Thread: ADS5294

Hi Team,

ADS5294 is being used in a project by customer. The project is for a radar system where there are 128 Tx channels. Eight ADCs are used which effectively provides 128 channels. The ADCs are interfaced to FPGA.

I came across the Sync feature where different chips can be synchronized for data rate. But, it is mentioned that this is possible with reduced output data rate in the datasheet. Can you please provide information on what is the limit on the output data rate?   Also, it would be helpful if the voltage level to be applied to the SYNC pin can be provided.

Thanks in advance.

-Best Regards,

 Suhas R C

  • 0
    TI__Genius 14540 points

    Hi Suhas,

    The tables labeled Absolute Maximum Ratings on pp5 and Digital Characteristics on pp9 indicate that all digital inputs can be 1.8V or 3.3V logic with a maximum of 3.6V allowed.

    In the Synchronization section of the datasheet, reduced output data rate implies a data rate that is lower than the sampling frequency (i.e. when decimation is used).  Therefore, using the lowest supported sampling frequency with the highest supported decimation rate will yield the low limit on the output data rate.

    Regards,

    Chrisitian

  • 0 in reply to Christian Yots
    TI__Intellectual 1690 points

    Hi Christian,

    Thank you for your detailed explanation. The information is very useful.

    I will get back to you in case I have any questions.

    -Best Regards,

     Suhas  R C