DAC8568 sometimes won't update correct output

Hi Dong,

This is very strange. I will need some more information in order to be able to debug your issue.

Can you share the code sequence that you are using? A scope capture of the SPI frame for a single write, will also help me verify that interface is valid.
Are you using the internal reference or external?
What is the supply voltage? IO voltage?
What is the load at the output?
A schematic capture around the DAC would also be useful.

Below is the code sequence to write to the DAC8568.

#define COMMAND 0x03 // Command to write and update channel n

unsigned char Byte3 = 0;
unsigned char Byte2 = 0;
unsigned char Byte1 = 0;

// DACn: is the channel select
// DataValue: is the 16 bits counts
// DACn and DataValue are received from UART buffer

SYNC = 0; // Enable the DAC chip select on the Analog Output
// Split data in to 3 separate bytes
Byte3 = ((DACn << 4) | (DataValue >> 12)) & 0xFF;
Byte2 = (DataValue >> 4) & 0xFF;
Byte1 = (DataValue & 0xFF) << 4;

SPI0DAT = COMMAND; // Write the COMMAND to the SPI data register
while (SPIF==0); // Wait until the write complete. SPIF flag will set to 1
SPIF = 0; // Reset the SPIF flag bit

SPI0DAT = Byte3; // Write the 8 most significant bit to the SPI data register
while (SPIF==0); // Wait until the write complete. SPIF flag will set to 1
SPIF = 0; // Reset the SPIF flag bit

SPI0DAT = Byte2; // Write the 8 mid significant bit to the SPI data register
while (SPIF==0); // Wait until the write complete. SPIF flag will set to 1
SPIF = 0; // Reset the SPIF flag bit

SPI0DAT = Byte1; // Write the 8 least significant bit to the SPI data register
while (SPIF==0); // Wait until the write complete. SPIF flag will set to 1
SPIF = 0; // Reset the SPIF flag bit

SYNC = 1; //Disnable the DAC chip select


I don't have a scope to verify the signals. At first, I was thinking there might be some missing data or noise that cause the incorrect data written to the DAC input register. However, the scenario# 2 in my first post telling that data was loading correctly into the DAC input register (my thought) .

I have the same error either using internal or external(2.4V) reference.

The supply voltage is 3.3V from the MCU board and this the clock and MOSI are also 3.3V peak.

No load at the output. I feed the output directly to the AINn inputs of the MCU board

I'm testing the DAC8568 on a breadboard. I use 10uF and .1uF coupling cap at AVDD and 1uF and .1uF for reference. The MCU board is a C8051F120DK. Therefore, there are a lot of wiring between the MCU and the DAC chip. I don't have this kind of error when I test on the DAC8830.

Can you verify if the data is being latched on the falling edge or rising edge of the clock?