1:4 transformer coupling for ads42lb69

Hi Eben-san,

Thanks for your answer.

My customer is now evaluating  ADS42LB69 with 1:4 transformer on their own designed board.
And they reported on spurious problem.

There is a device for signal processing after the ADC, where they are looking at the spurious level of.
As they increased the input level of the interference wave, the level of spurious to be measured shows that  raise or lower.
They entered the interfering wave of 70.253 333MHz and measured the level to be output as a component of 70MHz.
The 6-order spurious waveform is as follows;

Also, the 8-order  and the 13-order spurious level are almost the same result.
Unfortunately it is not possible to get the spectrum waveform in their system at this time.
Sorry,  I got the limited information from my customer.

Do you know what is happening?
Is there any solution for this problem?

Thanks and regards,
Toshi

Could you please respond for my question?
If you need addtional information, please let me know.
I will discuss with my customer.

Thanks and regards,
Toshi

Toshi,

What is the impedance of the filter? How does slowing down the sample rate effect this problem? Is the customer using a low jitter clock? Is the power coming from switching power supplies? Is there any chance they can try the recommend transformer approach (shown below)? How is the problem effected by changing the IF frequency? Answers to these may help us figure out what is going on with this board.

Regards,

Jim 

Toshi,

Here is more info from the design team:

If we assume that

• dBm numbers on his board can be directly converted to dBFS by adding 10dB to it.

• 6^th order is nothing but HD6, 8^th order is nothing but HD8

then, at -60dBm (or -50dBFS) input at 70MHz, he is seeing -115dBm (or -105dBFS) HD6. For inputs strength < -75dBm (or -65dBFS), HD6 seems to be buried in noise floor.

From device behavior perspective, these numbers looks fine to me.

However, from customer’s application perspective, this behavior may not be desirable, since he may not expecting higher order HDs to pop up even in small amplitude.

But the HDs may as well be coming from driver –so there can be either ADC or its driver as culprit.

 

If we explore the possibility of tones popping up from ADC, the device employs spectrum cleaning algorithms (namely Dither) which might cause this higher order spurs to show up when signal strength is very small…tones may also result from algorithms which correct flash ADC offset.  Can the  customer change the SPI protocol to try design debug modes? This would use a 24 bit protocol instead of 16 bit.

 

How big is this opportunity for us? Is a system fix possible for him to implement? What is the application?

 

Regards,

 

Jim

Hi Jim-san,
I am sorry for the late response. I got the answer from my customer as below;

1. What is the impedance of the filter?
-> Since the differential input has been terminated with 200ohm unbalance,
I have designed in 200ohm unbalance.

2. How does slowing down the sample rate effect this problem?
-> Since the signal source is a VCXO, it is difficult to change the sample frequency.

3. Is the customer using a low jitter clock?
-> The clock source is the VCXO of differential output type.
The phase noise has been realistically soaking the best of things.

4. Is the power coming from switching power supplies?
-> The power is coming from the linear regulator which is connected to the output of
the switching power supply.

5. Is there any chance they can try the recommend transformer approach (shown below)?
-> I think that it is first necessary to take this evaluation data, but the plan has been delayed.
Because I need to return to do the evaluation by using TI evaluation board,
it is expected to take until the end of the year.

6. How is the problem effected by changing the IF frequency?
-> I do not consider to change the IF frequency to another frequency band because this is
requirements of the system specifications.

7. Can the customer change the SPI protocol to try design debug modes? This would use a 24 bit
protocol instead of 16 bit.
-> I do not know the details of the Debug mode. Can you tell me how to set?　

8. Is a system fix possible for him to implement?
-> Yes.

9. What is the application?
-> A communications equipment for defense.

Regards,
Toshi

Jim-san,
There is a correction on A1.

1. What is the impedance of the filter?
-> Since the differential input has been terminated with 200ohm balance,
I have designed in 200ohm balance.

Regards,
Toshi