Problem with SYSREF detection during Multiple ADC Synchronization

Layne Jakahi

Other Parts Discussed in Thread: ADC12J2700, LMK04828, ADC12J4000, ADC12J2700EVM

We are currently having issues with the ADC12J2700. We are trying to implement the Multiple ADC Synchronization procedure and we are unable to detect the Sysref correctly. Even with no Sysref present, the SysRefDet and DirtyCapture bits are always high.

To verify this problem with the SysRefDet and DirtyCapture bit, we separated the SYSREF_p / SYSREF_n from the LMK04828 on our board. We then pulled down the SYSREF_p and pulled up the SYSREF_n using a 100ohm resistor in both cases. The bias measured at each pin (19 and 20), was 0.6V and 1.2V, respectively. This would simulate SYSREF as being stuck low (no edge transistions).

The way we implemented the Multiple ADC Synchronization procedure is as follows (Each step refers to a single instruction cycle):

1) WRITE SysRef_Pr_En = 0

2) WRITE SysRef_Rcvr_En = 0

3) WRITE SysRef_Rcvr_En = 1

4) WRITE SysRef_Pr_En = 1

5) WRITE SysRefDetClr = 1 and ClearDirtyCapture = 1

6) WRITE SysRefDetClr = 0 and ClearDirtyCapture = 0

7) READ SysRefDet and DirtyCapture. #These bits are always read as “1” even after clearing.

Prior to disconnecting the SYSREF_p / SYSREF_n, our ADC12J2700 had already gone thru and passed Ibert testing @ 6GHz. All 8 lanes are working.

Right now our development team is at a stand still as we don’t know why the ADC is detecting an edge that doesn’t exist.

Has anyone seen this sort of problem before? Please assist.

Thank you.

over 9 years ago

0 Jim Brinkhurst1 over 9 years ago

TI__Mastermind 44680 points

Hi Layne

What you describe is unexpected behavior. I just repeated your steps 1-7 on a board I have in the lab and the status bits set and clear as expected.

To help me understand the full picture can you provide a little additional information?

1) Can you send a list of all configuration register writes being done, up to the beginning of the procedure listed above?

2) Can you give the full register data write and read values (all 8 bits) for the steps 1-7 above?

I'll be out of office Friday on vacation but will follow up as soon as I can when you send more information.

Best regards,

Jim B

0 Layne Jakahi over 9 years ago in reply to Jim Brinkhurst1

Intellectual 820 points

Hi Jim
Thanks for the quick response. Below is what you are asking for:

//we are using static_address mode, the second parameter of the write_adc12J4000_reg is the reg address, the third parameter is the reg value.

write_adc12J4000_16bit(SPI_SS_ADC2, 0x000, 0xBDBD); //register reset(self clearing), after reset, chip is in streaming mode with address ascend.
write_adc12J4000_16bit(SPI_SS_ADC2, 0x021, 0x0040); //Power on Reset
write_adc12J4000_16bit(SPI_SS_ADC2, 0x021, 0x0140); //Power on Reset, edge triggered reset.
write_adc12J4000_16bit(SPI_SS_ADC2, 0x010, 0x0100); //set static_addr mode.

/**********************************************************************************************/

write_adc12J4000_reg(SPI_SS_ADC2, 0x201, 0x0E); //JESD_CTRL1; Disable JESD, before altering any parameters in JESD_CTRL1 and JESD_CTRL2.
write_adc12J4000_reg(SPI_SS_ADC2, 0x201, 0x0A); //set JESD_CTRL1: No scramble, K =3, DDR set.
write_adc12J4000_reg(SPI_SS_ADC2, 0x202, 0x44); //set JESD_CTRL2: Ramp test mode.

write_adc12J4000_reg(SPI_SS_ADC2, 0x050, 0x0E); //initiate a calibration set CAL_SFT =1, self cleaning.

write_adc12J4000_reg(SPI_SS_ADC2, 0x201, 0x0B); //Enable JESD

//power down sequence
step1: write_adc12J4000_reg(SPI_SS_ADC2, 0x030, 0x80);
step2: write_adc12J4000_reg(SPI_SS_ADC2, 0x030, 0x00);

//power up sequence
step3: write_adc12J4000_reg(SPI_SS_ADC2, 0x030, 0x80);
step4: write_adc12J4000_reg(SPI_SS_ADC2, 0x030, 0xc0);

step5: write_adc12J4000_reg(SPI_SS_ADC2, 0x030, 0xF0);
step6: write_adc12J4000_reg(SPI_SS_ADC2, 0x030, 0xC0);
step7 u8 reading = read_adc12J4000_reg(SPI_SS_ADC2, 0x031);

0 Jim Brinkhurst1 over 9 years ago in reply to Layne Jakahi

TI__Mastermind 44680 points

Hi Layne

I presume the value you read back from register 0x31h is always 0xC7h, indicating that both the SysRefDet and Dirty Capture bits are set.

I did see an issue (perhaps unrelated) with your setting of Register 0x201h.

K=3 is not a legal setting for DDC Bypass (decimation = 1) mode. 4 is the minimum allowed value.

For scrambling disabled, differential sync and K=4 or KM1=3 this register should be at either 0x0Eh when the link is disabled, or 0x0Fh when the link is enabled. 0x0Ah and 0x0Bh are illegal settings for DDC Bypass mode.

Having said that, I tried to reproduce the problem you are seeing with my lab setup and K=3 and still cannot get the detection bits to stay set. Once cleared they stay cleared until I disable and re-enable the receiver and processor.

That seems to leave the SYSREF input as the possible cause. When you apply the bias to the SYSREFp and SYSREFn pins using resistors, are you measuring right at the device pins? Is there any other circuitry that could be affecting the voltage right at the pins?

One final question, is this on the ADC12J2700EVM, or on a board of your own design? If it is your own board can you share the schematics for all ADC related signals?

I'm out for the rest of the day but will follow up Monday afternoon.

Best regards,

Jim B

0 Layne Jakahi over 9 years ago in reply to Jim Brinkhurst1

Intellectual 820 points

Hi Jim

Ok we tried the register setting change but no difference.

Yes those voltages, 0.6V and 1.2V are measured at the pins of the ADC. Since we disconnected this input from the on-board LMK, there is nothing else that could affect these pins.

Yes the ADC12J2700 is on our board design...not TI's demo board.

I can send you the pdf of the schematics if you provide me your email address as it is a proprietary design and I wouldnt want to just post it here.

Right now we are trying the same settings on the 2nd on-board ADC to see if we get the same results.

0 Layne Jakahi over 9 years ago in reply to Layne Jakahi

Intellectual 820 points

Hi Jim
Okay we figured it out just now. It has to do with the SPI commands that we are sending to the chip. We were using the STATIC SPI 32bit transactions but instead of making the 1st byte the same as the 2nd byte, we were sending 0's for the first byte. This must have got the SPI state machine in the ADC confused. Once we corrected this , it works as expected. Thanks for all your help. Its greatly appreciated. We have incorporated your suggestion about register 0x31h.

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Problem with SYSREF detection during Multiple ADC Synchronization