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DAC5688 PLL Questions

guodong mei
Prodigy 90 points
Other Parts Discussed in Thread: DAC5688

Hello, 

1). I use DAC5688 in External Clock Mode. the PLLEnable=disabled. PLLSleep = sleep. 

Do I still need to concern about the PLL_range and PLL_gain, PLL_m, PLL_n settings? 

2). My Input clock is 250MHz. If using internal interpolation =1 on the DAC5688 chip, that means the output clock is 250MHz. which exceeded the specified 160MHz Max CLKO output. I saw that the output signals are not continued.   the waveform looks like this. Is it because that the DAC output clock exceeding the 160MHz ? 

Thanks! 

Mei guodong 

  • 0
    TI__Mastermind 20541 points

    Hi Mei,

    Yes, that might be causing the issue. Have you tried to lower the clock frequency? Do you still see this behavior when your input clock rate is below 160MHz with 1x interpolation?

    I would recommend using interpolation to lower the CLKO output rate.

    Regards,
    Neeraj Gill

  • 0 in reply to Neeraj Gill
    Prodigy 90 points
    Hi Neeraj Gill,

    thank you for your reply.

    yes I did have tested with lower sampling clock i.e. at 200MHz or 230MHz Ext Clock to DAC5688(interpolate=1), the waveform are very good. Only when at 250MHz clock, it becomes bad.

    BTW, I used Half Data Rate Input mode, as I only have one channel output.

    I read some other forum threads, in half data rate and interpolate =1, at 250Mhz, the output CLKO should becomes 125MHz. this is within the spec, I am wondering why still have the issue.

    Do you have any suggestions regarding setting the PLL_range, PLL_gain? Even if I set PLL disabled, and PLL Sleep = Sleep mode, do I still need to set PLL_range, PLL_gain?

    thank you & Regards,
    Mei Guodong
  • 0 in reply to guodong mei
    TI__Mastermind 20541 points
    Hi Mei,

    In external clock mode PLL is not used so you do not have to worry about PLL_range and PLL_gain. Please make sure you are setting the register according to TABLE 5 on page 33 of the datasheet. We also recommend to buffer the CLKO.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    Prodigy 90 points

    Hi Neeraj,

    I would like to update you we solved this issue. It turns out that we need to use an external bandpass filter to filter the high order harmonics before acquire in another ADC. We were using a 3.2GS/s ADC and thought that has sufficient bandwidth to not have aliasing, however it is good to have a BP. 

    Adding a BP filter makes the signal much smoother. 

    Thank you for your support!

    Best Regards,

    Mei Guodong