Hello,
I am working on a design that uses the DAC5675A as a DDS output at 20MHz. We are feeding the DAC with a 50MHz clock from a TCXO. It is unfavorable as it is close to the Nyquist, but we could not use the PLL in the FPGA to bring the sample frequency up without degrading the phase noise. Phase noise and SFDR is important in our application.
At 20MHz output, we see a clean 20MHz that we can filter out the aliases as expected with good phase noise. When we try to change the output to 20.1MHz or any other frequency, we start to see very low frequency spurs at the DAC output. The spurs are about 120Hz away from the main carrier, and they look to be aliasing with something. We basically see a picket fence of spurs very close in to the carrier, maybe more than 10 on each side.
I noticed that the data sheet lists SFDR at 100MHz clock, but then the output is at 19.9MHz. Is there a reason why the 20MHz region may be specially susceptible to noise/spurs, etc.?
Any ideas or recommendations on debugging this problem?