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DAC3484 SPI Programming problems

Arvind Bhat
Prodigy 235 points

Other Parts Discussed in Thread: DAC3484, DAC3482

 

Hello,

 

 

I am using DAC3484 for an application and running into some SPI programming issues.  I have tried to provide as much details possible below.

 

 

The DAC setup is as follows: Quad Channel Mode, Interpolation by 4, Dual Sync Source Mode, NCO ON, Internal PLL OFF.

 

 

Also our application needs pulsed DAC output with repeatable phases per pulse. So we need to reset the NCO per pulse, which determine central frequency of the pulse. So the Frame input is periodic and follows the datasheet recommendation of fdataclk/(n x16). Our system is configured such that all clock signals (Fdataclk, Fdacclk, Fostr and Fframe) are stable and provided to the DAC before the SPI programming routine starts in the FPGA.

 

My DAC synchronization registers are configured for Dual Sync Source Mode as follows:

 

X"1E9999", %% Register x1E, SyncSel QMC Offset/ Correction set to  sif_sync OR auto_sync via reg write
X"1F2210", %% Register x1F, SyncSel Mixer set to OSTR, NCO and Data Formatter to FRAME
X"202400", %% Register x20, Syncsel FIFO, input sync(FRAME),output sync (OSTR)

 

 

I follow the programming sequence described in datasheet, page-72 and Table-10.  I follow the steps in Table-10 and reach the stage when i have to read the alarms. This is what i observe:

 1. When i read the alarm in Reg 0x05, i know that i have provided the periodic Fframe and Fostr to the FIFO. When i read the alarm i see alarms_from_fifo(2:0) = 001 (2 away) or 011 (1 away), but never 000. Since there is no FIFO collision detected i consider this as acceptable and complete the SPI routine, start sending LVDS patterns out and the DAC output look good on a spectrum analyzer. Are the observed alarms_from_fifo(2:0) values OK ? Should it always be 000?

2. Very rarely i see alarms_from_fifo(2:0) = 1XX, or collision detected. In this case i keep clearing Reg 0x05 and keep reading back Register 0x05, hoping that the alarm goes away with the next Fframe pulse. But my routine is stuck, as it always sees 1XX. What is the best procedure to re-synchronize the FIFO? Should i clear the all FIFO sync options in Reg 0x20, reprogram it, and then read the alarms again?

I would highly appreciate your feedback on this issue.

Thanks,

AB

  • 0
    TI__Guru* 82465 points
    Hi Arvind,

    Regarding your NCO requirement, I believe you may need deterministic latency with the DAC NCO enabled. Please take a look at the app note below for detail:
    www.ti.com/.../slaa584.pdf

    The app note also covers your questions regarding FIFO collision. Please take a look while I look at your questions in more detail.

    -KH
  • 0 in reply to Kang Hsia
    Prodigy 235 points
    Hello KH,

    Thanks for the app note reference.

    For the NCO synchronization i do follow the Fostr and Fframe guidelines in the app note Section 3.4, and i get deterministic NCO phase/ latency at DAC output.

    For dealing with FIFO collisions in Dual Sync Source mode, the figure 29 in the app note seems to be the best reference. So if i read that figure correctly, i need to keep changing the Read-Pointer (RP) position in my SPI routine via Register 0x09 fifo_offset(2:0), until the write-pointer (WP) to RP gap increases. Is that correct ?

    But, my general question is, if it is OK to have 2_away and 1_away condition, but no collisions, and operate the DAC normally ? Or should i always try to have alarms_from_fifo(2:0) = 000, by constantly adjusting the RP position, and then start providing data patterns to the DAC ?

    Thanks,
    AB
  • 0 in reply to Kang Hsia
    Prodigy 235 points
    Hello KH,

    I am trying to reach out again and get a response. As per my previous post, my main question is, if it is OK to have 2_away and 1_away condition for the alarms_from_fifo(2:0) in Register 0x05, but no collisions, and operate the DAC normally ? Or should i always try to have alarms_from_fifo(2:0) = 000, by constantly adjusting the RP position, and then start providing data patterns to the DAC ?


    Another question related to NCO.... The DAC3484 has coarse mixers which can generate Fs/2, Fs/4 and Fs/8. If i disable the NCO and use these carrier frequencies, how can i sync them for repeated phase/ latency ? I do not see any explicit sync source for these coarse mix carriers. Are they synced with the same sync source as the double-buffered mixer in Register 0x1F ? Is there relative multi-DAC synchronization advantages/ disadvantages of using coarse mixer carrier v/s NCO ?


    Thanks,
    AB
  • 0 in reply to Arvind Bhat
    TI__Guru* 82465 points
    AB,

    This depends on the end application. If your system consist of single DAC3482 device and do not require multi-DAC3482 devices synchronization, then the optimal FIFO configuration is adjust the RP until no collisions occurs. This will ensure optimal FIFO buffer in case there are occasional DATACLK/DACCLK lag/lead situation. Once you detect any FIFO alarms, these are indications that either clocks are moving and the system may not be stable.

    If you system requires multi-device synchronization, then the FIFO will be needed to absorb the latency difference among the multiple data bus to the multiple DAC devices. The read pointer will always have to be in the same place to ensure the right data position are released at the same point. The input pointer is used to absorb the bus latency difference. Thus it is possible that you may get certain alarms since the FIFO positions absorbs the delay differences among the DAC.

    See section 2.3 and 2.5 of the app note that I have mentioned.

    The Fs/2, Fs/4, and Fs/8 coarse mixers have preconfigured mathematics and are synchronized by the internal clock divider. If your application need multiple device synchronization, then you will have to be in dual sync sources mode where the OSTR is used for common device reference clock on the digital side. These mixer blocks will be synchronized by default.

    See section 3.3 for detail.