• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 725 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

question regarding to DAC3XJ8X GUI program

Jung HY
Prodigy 10 points

Other Parts Discussed in Thread: DAC37J82

Hi all
Basically I have purchased DAC37J82 EVM.
In the SERDES lane testing section from the image below (red box), 
I am wondering how it works or operate by using SERDES Test Pattern
Is there the way to see or check the output from the setting of SERDES Test pattern on the screen?
Also, Can anyone tell me what Lane ID in "lane configuration" means?
If i select  RX0 on GUI, does it means that RX0P/N can be used in DAC37J82 PIN?
Another concern is that the provided sequence in "8.3 initialization set up" is necessary to follow ?
Last question is
If I use default setting parameter except SYSREF & SYNC & clock output once I set up the clock parameter (using onboard clocking mode),
is there any problem to use the setting parameter on the DAC board?
I appreciate any help or comment
Thank you
  • 0
    TI__Guru* 82805 points
    Jung,

    For the SERDES lane testing, you may perform basic testing of PRBS patterns or simple 0/1 toggle on the serialized data line for each of the 8 SERDES RX lanes. For detail, please refer to section 7.4.2.

    The output of the pattern verification test will show up on the ALARM pin. This is a simple PASS/FAIL test. Each test looks at one of the eight lanes at a time.
    If you want more advanced testing such as counting the amount of errors or performing eye scan (to see the receiver eye diagram), you will need to access the advanced test mode through JTAG. I will have to send you additional documents, which is still in draft at this point.

    We recommend that you follow the initialization set up to ensure all the digital logics and JESD blocks are initialized correctly before data transmission. This will ensure the correct logic state is set up to avoid transmission error.

    Lastly, I do not see any issue on using the preconfigured DAC registers without the on-board clock chip registers. As long as you can ensure that you own clocking circuitry can duplicate the same DACCLK and SYSREF requirements, your system should work.

    -Kang