Missing information in DAC3151 datasheet

Hi,

The datasheet for that whole family of DAC devices is in the editing stage to fix typos, omissions, and errors.

The DACCLK does not have a specification section, so that is one of the omissions.  The DACCLK is expected to be driven by an LVPECL clock driver, so the input specs for DACCLK would reflect LVPECL specs.   Our design manager pointed out to me that the DACCLK input circuitry is the same design as the DACCLK input for the DAC3283, and is in the same CMOS process, so the datasheet specs for DACCLK in the DAC3283 would be what we add to the DAC3151 datasheet.  In particular he states:

The DAC3174 clock circuits are the same schematic as the DAC3283.  From the DAC3283 datasheet, the table on page 8 has the clock input details, and figure 50 on page 44 shows the circuits and internal biasing.

DATACLK on the other hand is expected to be an LVDS signal from the FPGA that also drives the LVDS data bus.   DATACLK is expected to be the exact same frequency as DACCLK, but of arbitrary phase relationship to DACCLK.  The presence of the FIFO in the DAC3151 is there to absorb any phase difference between DACCLK adn DATACLK. 

In the two-channel versions of this DAC family the DATACLK is dual data rate, DDR.  The sample data for one of the channels is on the rising edge of the DATACLK and the sample data for the other channel is on the falling edge of the DATACLK.   In the single channel versions the DATACLK does not change - it is just that the falling edge data is ignored since there is not the seconf channel. 

DATACLK and DACCLK need to be exactly the same frequency or else the input FIFO would eventually overflow or underflow.   The expected application is that the DACCLK comes from some clean low-jitter clock source, and a copy of that clock is provided to the FPGA which uses it toclock out the sample data along with a copy of that clock as DATACLK.    The FIFO in the DAC means that there need not be a concern to match the output data of the FPGA to the DACCLK edges - the FIFO takes up the phase mismatch between DATACLK and DACCLK.

In addition, there are SPI registers in the DAC3151 that allow for delay to be added to the clock or to the data signals inside the DAC to adjust the setup/hold timing to match what your FPGA can provide.  That also is not completely documented in the current datasheet but will be fixed in the revised datasheet.   The register Config3 has a number of 3-bit fields that can be set to delay the clock or the data in steps of approximately 80ps.  Bits 6:4 and 9:7 are shown as reserved and that is a mistake.  Bits 15:13 control the delay for half of the bus for the data and bits 6:4 and 9:7 control the delay for the other half of the databus and the Sync input.   So bits 6:4 and 9:7 should be set the same way as bits 15:13.    The difficulty in explaining those register bits arises because the 14bit versions of these devices offer a mode to split the input bus into two separate 7bit DDR busses and it becomes messy trying to explain in text which bits of Config3 go to which input delays.  It is easier with a picture, which we will do with the new datasheet.

Our EVM for the DAC3151 through DAC3174 family will connect with our TSW1400 pattern generator card and we can operate that system up to the full 500Msps.

Regards,

Richard P.