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DDC 264 evm 20 bit ADC interfacing problem

Panos Groumas
Prodigy 65 points

Other Parts Discussed in Thread: DDC112, DDC264, DDC264EVM

Hi,

currently we are using DDC 264 to digitize current signals coming from an array of photodiodes . We have
umounted the specific surface mount resistors on the analog board (we have the channel mapping) and soldered wires feeding the
photodiode currents.

I can read the signals with the software provided by TI, but I would like to develop my own program in Labview
that controls the DDC 264. I know that I should use USB_IO_for_VB6.dll and call it in Labview, but so far I haven't
managed to properly call the functions, control it and send or retrive data. The information regarding the functions in the dll's user guide is not very detailed.

Reading other threads in the forum, I found out that there is a FPGA register opcode mapping file available
(DDC_FPGA_register_opcode_map.xls ) for another device (DDC112). Is it possible to share the mapping of the FPGA registers
and their opcodes for DDC264?

Any information or help on how to get it working with Labview would be greatly appreciated.

Thanks in advance

Panos

  • 0
    TI__Guru 50036 points
    Hello Panos,

    We have received your inquiry regarding the DDC 264 and hope to have some answers back to you shortly.
  • 0
    TI__Guru 66550 points
    Panos,

    Thanks for contacting us. Let me look into a more concise DLL guide for you. At the moment you can use the other OP code document you have as it should be the same (if not very similar) to the OP code document for the DDC264. The main FPGA code behind the two different boards is very similar.

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 65 points
    Thank you Adam for your quick reply.
    I have managed to read the registers and their values using the WriteFPGARegsC function from the dll file. The mapping is indeed very similar to the DDC11xEVM as you have stated. When I finish the mapping I would like to share it in this thread if the moderators don't mind, so to confirm that I have not mistaken something and also to be available for others.

    However, I have not managed to change the register values through Labview. I give the new values in the form of an array with RegsIn argument (as they are given as output using RegsOut), but when I read them, I still get the old values. Does it have something to do with the RegEnable argument?

    I will perform more tests during the week and come back to you.

    Thanks again

    Panos
  • 0 in reply to Panos Groumas
    Prodigy 65 points
    OK,
    I have finished mapping most of the registers and I now know that you have to enable (set bit value to 1) the specific register in order to change its value. Below you can find the mapping and the default values (it follows the style for DDC11xEVM posted elsewere in this forum).

    I was not able to figure out the mapping of some registers, specifically registers 15 , 1E, 1F, 22. Additionally, I was not able to figure out which registers determine the channel setting, I could not change it through the format register as it is the case for DDC11xEVM.

    Could you please confirm that the mapping is correct, tell me which register changes channel count and provide the functionality and default values of these registers (15 , 1E, 1F, 22)?

    Register
    0100 - CONV Low Int - MSB (0 * 2^16=0)
    0206 - CONV Low Int - midSB (06h = 6d = 6*256 = 1536)
    033F - CONV Low Int - LSB (3Fh = 63) 1536+63 =1599 default CONV Low value)
    0400 - CONV High Int - MSB (0 * 2^16=0)
    0506 - CONV High Int - midSB (06h = 6d = 6*256 = 1536)
    063F - CONV High Int - LSB (3Fh = 63) 1536+63 =1599 default CONV High value)
    0777 - CLK (High) (Low)
    0800 - DDC CLK Config (1 - running , 0 - low)
    0910 - Format (10 - 20bit, 00- 16bit)
    0A00 - DCLK (High) (Low)
    0B01 - DCLK Config (1 - running , 0 - low)
    0CFF - nDVALID Ignore count (FFh = 255d)
    0D00 - nDVALID read count - MSB (0 * 2^16=0)
    0E04 - nDVALID read count - midSB (04h = 4d = 4*256 = 1024)
    0F00 - nDVALID read count - LSB (0h=0d) 0+1024+0 = 1024 readings = 512 readings per A side and B side

    1000 - Couldn't find functionality, value didn't change
    1100 - Couldn't find functionality, value didn't change
    1200 - Couldn't find functionality, value didn't change

    1332 - DCLKWait (MCLK) - MSB (32h = 50d=50*256=12800)
    14C8 - DCLKWait (MCLK) - LSB (C8h=200d , 12800+200=13000)

    1501 - ????

    1601 - Hardware trigger (disabled=0, enabled=1)

    1700 - Couldn't find functionality, value didn't change
    1800 - Couldn't find functionality, value didn't change
    1900 - Couldn't find functionality, value didn't change
    1A00 - Couldn't find functionality, value didn't change
    1B00 - Couldn't find functionality, value didn't change

    1C07 - DDC config register bits [15:8] Bits 15:12-> 0 0 (CLKDIV) 0 , Bits 11:8 -> 0 (Range[1]) (Range[0]) (Format)
    1D00 - DDC config register bits [7:0] Bits 7:4 -> (SPEED) 0 0 (SLEW), Bits 4:0 -> 0 0 0 (TEST)

    1E01 - ????
    1F01 - ????

    2033 - CLK_CFG (High)(Low)

    2100 - Couldn't find functionality, value didn't change

    2201 - ????

    Moreover, I have read in some posts for DDC11xEVM that there are Labview VI modules available for interfacing with the EVM. How can I also get these VIs so I can see how to properly call the dll functions and be able to communicate with the DDC264?

    Thank you in advance

    Panos
  • 0 in reply to Panos Groumas
    TI__Guru 66550 points
    Panos,

    Please provide your email and we can discuss this.

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 65 points
    Hi Adam,
    thank you again for your prompt response. Much appreciated!

    I have send you a pm.

    Kind regards,

    Panos
  • 0 in reply to Adam Sidelsky
    Prodigy 25 points
    Dear Adam,

    May I ask the opcode of the DDC264EVM. I try the op code of DDC11xEVM, but some commands did not work. For example, "channel count", with the op code 091x, x should be range from 0 to F, whichi is the power of 2. But it seems did not work on DDC264EVM.

    I already made the clock low and clock high configuration work. So I think the communication USB between the PC and FPGA is fine, and I may use the wrong op code.

    Many thanks for your reply,

    Xiao
    ------
    xiao.li@indigomed.com