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DAC3482 - clocking the DATACLKP/DATACLKN input pins with a 1 GHZ LVDS signal

Dan Wieland
Intellectual 2625 points
Other Parts Discussed in Thread: DAC3482

We would like to use the DAC3482 for the “on-board” 32-bit NCO only.  We would NOT feed any data into the D0P-D0N through D15P-D15N data inputs. 

 We would like to clock the DAC3482 DACCLKP/DACCLKN clock input with 1 GHZ differential input clock.

 This is my question:

 What do I do with the DATACLKP/DATACLKN input pins? Can I clock them with a 1 GHZ LVDS signal?

Thanks

  • 0
    TI__Guru* 78324 points
    Dan,
    You would need to enable config45, bit0 constant input capability so the DAC ignores the LVDS data bus. Program config48 and config2, bit 1 for the correct data input and data format (2's vs. offset binary).

    Three things to note:
    1. the constant code is a DC value to the complex mixer/NCO. Either full-scale negative (i.e. 0) or full-scale positive (i.e. 65535) will result full-scale sine wave output

    2. TXenable (both software and hardware based) will be ignored at this point. Therefore, it is possible that the device output a strong tone to the rest of the signal chain at power up and potential damaged high gain devices like PA.

    3. Design recommends at least 64 DATACLK cycle to latch the constant input data code across the FIFO. Since you are clocking it at 1GHz, the input data code should get across without any issue.

    You may always test out the functionality and performance using the DAC3482EVM.

    -Kang