Hi
I'm interfacing with two ADS8688 that are daisy chained via the SPI bus on an AM3352. However the fact that they are daisy chained is most likely irrelevant to my problem. Here is the schematic:
adc1 = ADS8688(o)
adc2 = ADS8688(o)
# digital connections
connect(adc1["DAISY"],o["DGND"])
connect(adc1["SDO"],adc2["DAISY"])
connect(adc2["SDO"],o["ADC_SERIAL_OUT"])
connect(adc1["~CS"],adc2["~CS"],o["ADC_CHIP_SELECT"])
connect(adc1["SCLK"],adc2["SCLK"],o["ADC_SERIAL_CLOCK"])
connect(adc1["SDI"],adc2["SDI"],o["ADC_SERIAL_IN"])
connect(o["ADC_SERIAL_OUT"],S("spi0_d0"))
connect(o["ADC_SERIAL_IN"],S("spi0_d1"))
connect(o["ADC_CHIP_SELECT"],S("spi0_cs0"))
connect(o["ADC_SERIAL_CLOCK"],S("spi0_sclk"))
I am running the SPI controller in SPI_MODE_1 (CPOL=0 and CPHA =1) at 5MHz. I perform a PROGRAM register write with 3 bytes (0x03 0x91 0x00) as a test. In other works PROGRAM register 0x01 (AUTO_SEQ_EN) is being written with data 0x91 (enable channels 7, 4, and 0). I can see the data be clocked out correctly by the SPI master on my oscilloscope for the first 2 bytes: bits change on the rising edge and the ADS8688 samples the signal on the falling edge. So far so good.
The last byte the ADS8688 clocks out the data (0x91) which means it successfully read my command/data however the bits are change on the falling edge of the clock! In fact, according to the datasheet this is what is suppose to happen:
8.4.1.1.3 SDI (Input)
SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for
device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line
are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made
to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of
the CS signal.
8.4.1.1.4 SDO (Output)
SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data
output frame varies depending on the register setting for the SDO format; see Table 13. A low level on CS
releases the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the
output data stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits
on every falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z
state when CS goes high.
but that has to be wrong because CPHA=1 means that both the slave and the master should be sampling data on the falling edge and clocking out on the rising edge. However, if the ADS8688 is clocking and sampling data on the falling edge how is the master suppose to sample it? The phases for the MOSI and MISO signals are opposite which is not standard SPI, right?
I've stared at my oscilloscope traces, and I just can't see how this is suppose to work. What's going on? Does the ADS8688 have a huge bug?
