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DAC38J84 FMC Signals

Paul Joseph
Expert 2795 points
Other Parts Discussed in Thread: DAC38J84, LMK04828

We are working on a combination of a Xilinx board and the TI DAC3XJ8X EVM (with the DAC38J84 device), and need some clarification on the purpose/use of the following signals that are connected to the FMC connector:

 

1.  FMC_SEN_DAC

2.  CLK_LAO_0P and CLK_LAO_0M

3.  FMC_SEN_LMK

4.  FMC_B5

5.  FMC_B6

6.  FMC_DIR_CONTROL

Please advise and thank you

  • 0
    TI__Intellectual 1440 points

    Hi, Joseph:

    1. CLK_LAO_0P and CLK_LAO_0M
    is the Serdes clock reference for Xilinx FPGA which is provided by LMK04828.
    2. FMC_SEN_DAC, FMC_SEN_LMK,FMC_B5,FMC_B6, FMC_DIR_CONTROL is the SPI interface between FPGA and CPLD through FMC interface.
    FMC_SEN_DAC: DAC SPI enable signal;
    FMC_SEN_LMK: LMK SPI enable signal;
    FMC_DIR_CONTROL: Read or Write control signal;
    FMC_B5,FMC_B6: DAC or LMK read back data signal which is used with FMC_DIR_CONTROL signal;

    I have attached the file used in CPLD on the DAC38J84, you can try to decode it and verify that the SPI interface works as you needs.

    Thanks
    Yarn.

    DAC38J84_CPLD.rar