ADS42LB69 CLKOUT trouble

Masa,

What mode is your output, DDR or QDR? What is the level of the CLK input signal? It looks unstable when your enable signal is going high? How do you have SYNCINP/M connected? What type of power supplies are you using? Do you notice this issue at a slower clock rate? Have you tried different clock amplitudes to see what effect this has?

Regards,

Jim 

Jim,
Thank you very much for your prompt advices. CLK input is 1.8Vpp. The rate was varied from 10MHz to 250MHz. I attached wave the worst case at 250MHz.

Please let me check other points you advised and will report you.

Best regards,
Masa

Masa,

What is the disable/enable signal you show? Is this the reset going to the ADC?

Regards,

Jim

Hi Jim,

I would like to respond to your previous advices.

output mode: DDR

SYNCINP : connect to GND

SYNCINM: connect to AVDD (1.8V)

power supply type : use LDO for both 1.8V/3.3V

clock rate: tested from 10MHz to 250MHz. Unstable time was 70us at 10MHz clk rate (20us at 250MHz)

And I will correct and report exact signal measurement point of CLKIN and Disable/Enable showed in the first my report. 

Best regards,

Masa

Hi Jim,

Please refer below drawing. The input clock source is distributed by clock buffer. One output is connected to ADS42LB69, and another is monitored by scope with AC coupled with 50 ohm terminators. 

Another question on the Disable/Enable, it is not connected to ADS42LB69 but just monitor at source clock generator. 

I would appreciate for your support,

Masa

Masa,

Your drawing is missing the LVPECL termination resistors. Is this how you have it on your board? If so, the clock will not be driven properly.

Regards,

Jim

Jim,

Clock Source Output Impedance is 50ohm, then receiving it with 100ohm termination at CLKP/M (ADS42LB69), it was thought that 150ohm resistors are not necessary. Was it incorrect? Why 150ohm is required? 

Best regards,

Masa

Masa,

For information regarding LVPECL termination, see application report SCAA059C on the TI website. Section 1.1 describes why the 150 Ohm pull downs are required. Most LVPECL devices will not operate without this.

Regards,

Jim

Jim,

The clock buffer is AD9508 in HSTL output mode. Do you think that CLKIN wave in my first report was not good and pull down resistors before ac couple capacitors should be required?

Best regards,
Masa

Jim,

Do you think if the below CLKIN (in red circle) wave (DC factor) is a troublesome for ADS42LB69 clock input?

I found the below description in AD9508 datasheet.

Thank you for your advice in advance.

Best regards,

Masa

Masa,

Yes. The amplitude looks shifted. What is the source?

Regards,

Jim

Jim,

The source is AD9508 (sorry for not TI part).

Best regards,

Masa

Masa,

What mode are you using, LVDS, HSTL, or CMOS?

Regards,

Jim

Jim
It is HSTL.

ref: e2e.ti.com/.../462616

Best regards,
Masa

Masa,

Try changing it to LVDS and AC couple the outputs.

Regards,

Jim

Hi Jim,

Sorry for slow response.

Is it just change AD9508 mode to LVDS without chnaging registor network? And would you kindly let me know why this try will expect to work?

And is "ADC latency + tPDI" an expeting time to get stable CLKOUT afetr CLKIN start oscilating?

Best regards,

Masa

Masa,

Changing to LVDS should give you proper termination for the clock. What do you mean by "changing register network?" Did you mean resistor network? I will get you an answer about your other question.

Regards,

Jim   

Jim,

It was a typo and should be resistor network -sorry.

I would like to make sure the right resistor network to AD9508.

Best regards,

Masa

Jim,

I would like to confirm if "ADC latency + tPDI" should be an expecting time to get stable CLKOUT afetr CLKIN start oscillating at first.

Then, what RC network should with which mode should be for connecting to AD9508?

Best regards,

Masa

Masa,

Reference figure 116 of the data sheet for clock termination. Set AD9508 to LVDS mode. I will get back to you on the other question.

Regards,

Jim