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Is SYNC?SYSREF absolutely necessary for DAC37J82

Gordon Hardman1
Intellectual 540 points
Other Parts Discussed in Thread: DAC37J82, DAC38J82, LMK04828

I am working on a design for a FPGA driving a 16 bit DAC, DAC37J82. There are 4 lanes of JESD204B available, and I am wondering if the attached clocking scheme will be adequate. From the DAC data sheet:

"In many applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely
synchronized such that their outputs are phase aligned. The DAC37J82/DAC38J82 achieves the deterministic
latency using SYSREF (JESD204B Subclass 1).


SYSREF is generated from the same clock domain as DACCLK, and is sampled at the rising edges of the device
clock. It can be periodic, single-shot or “gapped” periodic. After having resynchronized its local multiframe clock
(LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the signal on
the SYSREF input can be enabled and disabled via the SPI interface."

Thus it appears that since I am only using a single device, it should be possible to use the scheme below. The LMK03033C was suggested by the TI Web clock accessory. We are not pushing the DAC near its limits in terms of frequency, but it is being used in an I/Q modulalor to produce 32APSK. SO although we do not yet have a good jitter specification, it appears the 200fs from the LM03033C will probably be adequate.

Any comments or suggestions for improvement much appreciated.

  • 0
    TI__Expert 4340 points

    Gordon,

    In general, the "SYNC" signal is always required for JESD204B interfaces. The application must use the SYNCBP/SYNCBN pins.

    The SYSREF signal is always required for a JESD204B subclass 1 interface if deterministic latency is desired. If the application can allow the latency through the DAC to be different each time you power up, then deterministic latency is not required and SYSREF may be optional, but this is device dependent. Some devices can startup the JESD204B link without requiring SYSREF but other devices cannot. The DAC37J82 does not require SYSREF signal (SYSREFP/SYSREFN) and the pins can be left unconnected.

    Regards, Josh

  • 0 in reply to Joshua Carnes
    Intellectual 540 points
    Josh,

    Thanks for that. This is my first JESD204B design. I see the LMK03033C has a SYNC input. It is single ended (CMOS?), but I assume I can put a LVDS line receiver there and use that with SYNCBP and SYNCBN?

    In this case, there is no requirement for deterministic latency on power up, so I propose to not use SYSREF.


    Gordon
  • 0 in reply to Gordon Hardman1
    TI__Expert 4340 points
    Gordon,
    I need to correct myself here. It appears that operation of the DAC37J82 without using a SYSREF signal has not been verified. For guaranteed operation, you must use a SYSREF signal.
    Note that the SYNC input on the LMK03033C is not related to the SYNC signal used between the DAC and FPGA JESD204B interface. The LMK03033C SYNC signal is used to synchronize the internal clock dividers of the clock chip. The SYNC signal on the DAC37J82 is specifically for JESD204 interface synchronization.
    Regards, Josh
  • 0 in reply to Joshua Carnes
    Intellectual 540 points
    Josh,

    Thanks for that. It may have avoided an expensive mistake. I take it from this that LMK03033C is NOT suitable for JESD204B use?

    If so, I wonder what is the lowest power clock chip that can be used with JESD204B? The eval boards seem to use the LMK04828, which uses around 1.9W, which seems very high when I only need to drive a DAC and an FPGA!

    Gordon
  • 0 in reply to Gordon Hardman1
    TI__Expert 4340 points

    Gordon,
    LMK03033C was not designed specifically for JESD204B applications (as opposed to the LMK04828), but it can still be used with JESD204B devices. The LMK03033C can be used to generate the required device clock and it can also be used to generate a SYSREF signal. Due to timing considerations, the LMK03033C may not meet setup/hold timing between the device clock and SYSREF at the DAC inputs, as required for determinstic latency, but this should not prevent its use for your application because it appears that deterministic latency is not required. 

    The SYNC input to the LMK03033C syncronizes the internal clock dividers and can be provided by an FPGA (or not used at all). Again, this is different from the SYNCB signal that is output from the DAC.

  • 0 in reply to Joshua Carnes
    Intellectual 540 points
    Josh,

    I think I had just reached the same conclusion! So I need 4 outputs, two each of SYSREF and CLK, and the DAC and the FPGA core get one of each. The SYNCB signal goes from the DAC to the FPGA core. Have I more-or-less got it straight? I see there are way to skew the various outputs by setting registers, so that eases layout, I guess. The dividers on the SYSREF outputs are set to the ratio determined by the LMC?

    I have a block diagram, but I can't find a way to attach it. (when you create a new post, there is that option).

    Gordon
  • 0 in reply to Gordon Hardman1
    TI__Expert 4340 points

    Yes, I think you are undersatnding things correctly.

    Regards, Josh