I am using ADS6129 ADC for my current project interfaced with Arria V FPGA. ADC would be configured in LVDS mode with a sampling rate of 250 Msps.
The clock input for the ADC is derived from the Arria V PLL FPGA.
The max jitter of the PLL is 250 ps (period jitter). What is the effect of output data of ADC for the specified jitter. Data sheet doesnt mention about the jitter specs of the ADC. Is the ADC capable of handling such a jitter and still produce outputs with high SNR?
