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DDC264EVM Integration time

Other Parts Discussed in Thread: DDC264EVM, DDC264

We have been successfully using the DDC264EVM to evaluate reading photodiodes at a 320 micro-second integration time.  It is straightforward to use a longer integration time, by changing the CONV hi and lo numbers, but we would like to use the 160 micro-second integration time, and this doesn't work. Is there a setting of the registers that can achieve this shorter integration time?

Or, is the board made with the slower version of the DDC264 chip?  Is there a way to tell?

Thanks.

  • Fritz,  we have received your post and will return with an answer soon.

    Thanks,

  • Fritz,

    Thanks for contacting us. I am the applications support for the DDC264 and would be glad to help you out.

    The EVM is capable of running the DDC264 at 6kSPS (160uS Tint) with the following settings:
    CONV Low/High Int: 1600
    CLK High/Low: 3 (this gives us a 10MHz CLK which you will see to the right once this field is updated)
    DCLK Hihh/Low: 0 (this gives us 40MHz DCLK so that we can readout all 256 channels within one CONV cycle)
    DCLK Wait: 1750 (suggested, this value can be changed in accordance with the readout rules stated in the datasheet and EVM User's Guide)
    Bit 7: 1

    After these settings are updated, you will need to click "Refresh All" so that the settings will be written to the FPGA and DDC264 devices.

    Please remember to click the "Update Plot" button below the timing display on the GUI to update the plot so you can check that the timing is correct.

    Regards,

    -Adam
  • This worked!
    Thank you very much for the details on the settings.
    Fritz