ADS8866 - Timing Requirement in Daisy-Chain Operation

Hiroshi Katsunaga

Mastermind 6480 points

Other Parts Discussed in Thread: ADS8866

Hello,

My customer have some questions about ADS8866.

[Q1]

Is my understanding correct ?

The specifications of the "tsu-CK-CNV" and the "th-CK-CNV" are to meet the following.

"SCLK must be low at the CONVST rising edge." (datasheet P.22)

Therefore it's no problem that SCLK is Low in the period when it's long enough in front of the CONVST rising edge like figure 50, and output SCLK after "tconv-max".

[Q2]

Do you have the specification between the CONVST falling edge and the SCLK falling edge of final bit ?

Is the following timing OK ?

Best Regards,

Hiroshi Katsunaga

over 9 years ago

0 Dale Li over 9 years ago

TI__Mastermind 45515 points

Hi Hiroshi,
For 1st question, you are right.
For 2nd question, there is a requirement "CONVST must remain high from the start of the conversion until all data bits are read", there is no direct time delay requirement between SCLK and CONVST, however, there is a minimum time requirement (2ns) for th-CK-DO (SCLK falling edge to current data invalid), also the maxmium time for td-CNV-DOhz (CONVST high or last SCLK falling edge to DOUT 3-state) is 13.2ns, so it's better that the time delay between SCLK falling edge of final data bit and CONVST falling edge is greater than 13.2ns, 20ns is a good practice.
Thanks.

Regards
Dale

0 Hiroshi Katsunaga over 9 years ago in reply to Dale Li

Mastermind 6480 points

Hi Dale,

Thank you for your fast response.

I understood your all comments.
Your comments are very clear.

Thank you for your support.

Best Regards,
Hiroshi Katsunaga

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ADS8866 - Timing Requirement in Daisy-Chain Operation