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Clocking for 50MSPS ADC

Fan Yi48
Prodigy 20 points
Other Parts Discussed in Thread: LMK00804B

Hi, everybody, I'm trying to implement a 50MSPS 12-bit ADC with FPGA. I'm new to high speed ADCs and after some research I'm confused about the clocking.

I find that most solutions for high speed ADCs use a VCXO to form a PLL for the clocking, and an XO as the reference clock. I don't understand why the PLL is necessary, can I just use an low-jitter XO to directly provide the clock to the ADC?

Thanks!

  • 0
    TI__Genius 12965 points

    Hi Fan,

    The clocking solution in some cases requires the ADC clocks to be locked to a system reference to ensure system level frequency accuracy (coherency & frequency accuracy measurements).  If there is no need to lock the signal to a reference then the clock driving the ADC can be free running.

    Some ADCs will also have internal PLL which it uses to generate internal clocks for data processing or for use in serial LVDS or SERDES digital interface clocks.  This PLL ensures the digital interface clocks are aligned to the ADC sampling clock.

    Ken.

  • 0 in reply to Ken C
    Prodigy 20 points
    Hi Ken,

    Thank you for answering my question. Yes I know that PLL is used to achieve synchronization, but I'm confused because I find that in some cases even if there is only one ADC, the VCXO and XO are used together in PLLs to clock the ADC. So is this an approach to further reduce jitter?

    In my case,for example, can I just use a LMK61A2 (although it's not 50MHz) directly connected to LMK00804B, and use two outputs of LMK00804B to clock the ADC and FPGA?

    Thanks,
    Fan
  • 0 in reply to Fan Yi48
    TI__Genius 12965 points
    It depends on the implementation. Some of the LMK devices also provide a means to use a cleaner reference to generate higher frequency clocks and clean up the jitter as well - this may improve your overall SNR performance. I think the LMK team can comment further on the jitter cleaning function of some of the LMK products.

    If you do not require referencing your sampling clock and signal source to a system clock for coherency reasons then you can use any source to drive the ADC clock.

    On some of the ADC EVMs a 10M reference is provided so that a system reference can be provided to external test equipment for tests which involve coherency. This source will ensure the onboard sampling clock will be locked to the same reference as provided to the external signal generator to drive the input of the ADC.

    If your clock is clean enough, then you can use it to drive the ADC and FPGA directly.

    Ken.