Alessandro,

Can you clarify if you need the TSW1400 firmware (Altera) or TSW1200 (Xilinx - legacy tools)?

Ken.

Hello Ken,

thank you for your quick reply, we are currently working with Altera FPGAs just  to test the ADS6425 EVM functionalities, but in the next few weeks we will move to Xilinx FPGAs, so if it is possible to have both the versions of the firmware would be very good things.

Alessandro

I will have one of the other engineers send you the reference design we id with the TSW1200 which was using a Xilinx FPGA.

Ken.

Hello Ken,

We are actually testing the ADS 6425EVM, with an external clock but without  applying any input signal to be acquired. After powering up we see a strange periodic sequence on all the output channels, even if we are not giving anything on the input. How can this be explained ? Is there some kind of pattern active in the chip? If yes, how can we change it? if we try change the control signals from the FPGA it does not change anything, are there some phisical components we have to remove?.

 

The current  board settings  on the power pins and on the jumpers are : 

Power :

 -P1 - P3   :  3.3 V

 -P2 - P4   :  GND

Jumpers:

 -J16 : 0 dB coarse gain int. ref.

 -J17 : DDR 2 wire

 -J18 : 14x rising edge

 -J19 :  DIV by 1

 -J20 MSB first, 2s comp.

Hi,

If you are using 2s complement mode then noise will cause a deviation around +/-0, this will toggle all of the bits.  Do you know the actual values?

Ken.

The signal has approximately an amplitude of 2.20 V. But the problem is, that such signal comes out even without connecting the input cables on the channels. When we connect them and we send the signal, nothing changes on the output, the sequence is always the same.

What signal is 2.20V? Where is it coming from the ADC?

The ADC should take in a CLK, analog input signal and output LVDS signals on the digital interface.

Ken

The signal is coming out from all the four LVDS output channels of the ADC,
Yes we apply an input clock but there are no analog input signal applied. It seems like the adc generates a periodic sequence on its own.

Hi

As I mentioned before the serial LVDS output will output a digital word even if noise is present. 2s complement format will have small signal noise deviations toggle all of the sample bits. These bits will then be serialized onto the serial LVDS outputs.

Is this digital pattern you are seeing the same repetitive sequence of 1 and 0, repeated over and over? Or just a sequence 1s and 0s?

How are you measuring the digital interface, with an LVDS receiver on the FPGA/logic analyzer or with a scope?

Ken.

Hi Ken,
the digital sequence is the same and repetitive, but is different for each channel.
We are measuring the signal using the logic analizer and also using a scope and probing the outputs directly on the LVDS connector on the board.
thanks

Hi,

if you are looking at the LVDS signals right off the EVM using a logic analyzer, then you should be able to dump a large capture buffer of the sample data bits to a file for analysis or post processing.  That is what we used to have to do years ago before we had FPGA-based capture cards to assist in the EVM evaluation.

Looking at your logic analyzer results, look at the frame clock signal first, before moving on to the data lines.  The frame clock signal is just like a fifth data line except that it has a known data pattern which in 2-wire 12bit mode will be 111000.   Make sure your logic analyzer is set up to use the bit clock in DDR fashion and is latching data on both rising edges and falling edges.  If you were losing half your data by using only rising edge then your frame clock would be something like 100 or 011 repetitive.    If you are not using the bit clock to do the sampling but rather letting the logic analyzer sample the data from an internal free-running higher rate clock then you could still look at the sampled bit clock and see when it goes from low to high and high to low that the frame clock at those edges should still paint out a fixed pattern of 111000.  

(don't be mislead by the silkscreen on the EVM that says 14bit.  That was printed for the case where this EVM supports the 14bit version of the device.  The 14bit device has an option to pad two extra zeros on the sample to make it 16 bit so it is easier to deserialize.  So that device has a 14b mode and a 16b mode.   When using the 12 bit device, there is still the option to pad two extra zeros to make a 14b pattern.  But a 12bit pattern is easier to deseriaize.    So the silk screen should really say 12b or 14b when using the ADS6425 instead of 14b or 16b - but with your EVM you can consider the 14b selection really means 12b.    Similarly, don't be fooled by that same selection saying rising edge.  The other jumper already selected DDR clocking so both edges are used, not just rising.   Jumper J18 can only choose rising or falling *if* jumper J17 didn't already select DDR.  So your jumper settings look correct to me. )  But there are many places where errors can occur before you begin to 'see' that frame clock pattern on your logic analyzer.  If the LVDS polarity of the clock or the data or both is inverted from what you expect, then that would mess things up.  The user guide for the EVM has the schematics of the EVM in it, so you can see if there were any inversions in the differential pairs that might have been done to make the routing from the ADC to the connector easier.

If you can 'see' the expected frame clock pattern in your logic analyzer data, then from that you could begin to analyze the captured data from the other four data channels as well.  You could save the data to a file and use a scripting language or Matlab or something to deserialize the captured data.    we used to do that with Labview code before we had the FPGA capture cards.    Every where you see the 111000 frame clock pattern, take those same 6 bits from each data lane, and since you are in 2-wire mode put two sets of these 6 bits together to get back to the 12 bit sample.  Then you could store a buffer of sample data for each channel for analysis.

Consider also getting one of our capture cards to verify the EVM is working as expected.  The TSW1400 and the TSW1405 come with a GUI that makes it easy to see the sample bits and then you can see the effects of idle channel noise making the lsb's toggle somewhat randomly, and offset error shifting the center code for the idle channel noise away from mid-scale slightly, and the effect of the offsetbinary/2'scomp selection on the appearance of the sampled bits.  The TSW1405 is cheap, but *much* easier than trying to do all this on the logic analyzer.

Regards,

Richard P.

Thank you Richard,

The Frame clock and the bit clock are good, but when i set the 1 wire configuration, 2 channels of the board are completely shut down, if i put a waveform on the input i don't see anything on the output, even if i make a measure with a scope, I have 0 V .

Regards

Please check J6 and J8: SCLK and SDATA. These can also be used to set the output to a fixed test pattern. Refer to data sheet page 11:
www.ti.com/.../ads6425.pdf

Ken.