Hello,
I have some questions about ADC12J4000.
[Q1]
- LMK04828B is configured as clock distributor in ADC12J4000EVM.
- The source of LMK04828B is MC10EP32D.
- The output of TRF3765 is devided by 2 by MC10EP32D.
I think there is 2 ways of phase relationship of the output of TRF3765 and the output of MC10EP32D.
Is phase relationship of the Device Clock and the SYSREF always satisfied with such way ?
[Q2]
My customer would like to use 4 of ADC12J4000s and 1 of TI DAC.
In this case, please tell me your recommended clock solution.
I considered the following suggestion.
- Device clocks of ADC12J4000s generate by TRF3765.
- SYSREFs of ADC12J4000 and DAC and FPGA and device clock of FPGA generate by LMK04828B (0-delay mode)
- Device clock of DAC generate by the other RF synthesizer.
- The references of TRF3765, LMK04828B and the other RF synthesizer are distributed by fan-out buffer.
- Setup / Hold between SYSREF and Device clock is adjusted by LMK04828B.
How do you think about that ?
Are there any good solution ?
Best Regards,
Hiroshi Katsunaga
