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ADC121 under 50ksps

Gaston Schelotto
Expert 2860 points
Other Parts Discussed in Thread: ADC121S021

Hello,

I'd like to run ADC121 at 4ksps but the datasheet specifies the performance within the 50ksps-200ksps range. Is it possible or I would working out of specifications? If it possible, what drawbacks should I take into account?

regards,
gaston

  • 0
    TI__Genius 16890 points
    Hi Gaston,

    I assume you are talking about the ADC121S021.

    There are two ways you can do this.

    1. You can run the clock at 80kHz (for 4ksps). There will be some sagging of the voltage on the internal sampling cap, but it will be minor. You are running the part out of specs, so none of the specifications in the datasheet will be guaranteed.
    2. Run the part with the clock within the specifications (1MHz to 4MHz) and then assert the CS pin at 250us intervals (4kHz). This will give you a 4ksps rate and no sagging of the voltage on the sampling cap will occur. The part will also be used within specifications with this method.

    Mike
  • 0 in reply to Michael Stout
    Expert 2860 points

    Hi Mike,

    Thanks for the feedback.

    Michael Stout said:
    I assume you are talking about the ADC121S021.

    Yes I'm talking about this part

    Michael Stout said:
    There are two ways you can do this.

    Well, I prefer to do as you suggested at point 2 to avoid unexpected behaviors. More questions in this regard:

    • I have to run the SCLK (1MHz to 4MHz) always or just when I assert the CS?
    • I've checked ADC121S101EVM User's Guide and by using the GUI you can do a single read data. I assume that when you click the 'Single Read' button the launchapad asserts the CS and reads the data by SPI with SCLK at (1MHz-4MHz). The SCLK is activated only when you get the SDATA. Am I wrong?
    • If so, SCLK runs always at (1MHz-4MHz) and I have to assert the CS to get the SDATA. Must the CS assertion be synchronous with SCLK?

    regards,
    gaston

  • 0 in reply to Gaston Schelotto
    TI__Genius 16890 points

    Hi Gaston,


    You only need to run the clock after the CS is asserted.  This is what the eval board does when you do a single read, it asserts CS and then starts the clock to do the writing and reading.


    Mike

  • 0 in reply to Michael Stout
    Expert 2860 points
    Hi Mike,

    All right, thanks for clarifying this. But

    This means that the single read of EVM is out of specs (50ksps to 200ksps)?
    I'm sorry but I still don't understand the impact of running the device under the lowest limit (50ksps) of the sample rate. Could you give more hints about this?

    regards,
    gaston
  • 0 in reply to Gaston Schelotto
    TI__Genius 16890 points

    Hi Gaston,

    As long as SCLK is between 1MHz to 4MHz the part will be within spec. (Note that a 1MHz clock translates to 50ksps (1MHz / 20 = 50ksps) and a 4MHz clock is 200ksps (4MHz / 20 = 200ksps)).  See Figure 3 in the datasheet.  The clock does not continuously need to run.  If you want a sample once a second, you can do the sequence shown in Figure 3, then wait for one second with CS high and the clock high, repeat Figure 3 again, and so on.  You now have a rate of 1sps but you are still running the clock at a rate between 1MHz and 4MHz so the part is being used within specifications.

    Mike

  • 0 in reply to Michael Stout
    Expert 2860 points
    Mike, thanks for your detailed explanation.

    regards,
    gaston