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ADS8881 connection to C6748 McASP

EngH060
Intellectual 365 points
Other Parts Discussed in Thread: ADS8881

Looking for confirmation that 4 ADS8881 ADCs could successfully be connected to the McASP of the C6748.   I couldn't find any documentation that spoke to interfacing an SPI converter to the McASP. If you have any it would be most helpful to receive it.  

Here are a few details of what needs to be accomplished and what seems to be a probable interface approach. 

- the system needs to simultaneously sample all 4 converters.    

- the converters need to sample at approx 500KSPS.

- only the 16 most significant bits of the 18 converter bits are required.

- from a read of the spec for the MCASP and the ADC it would appear they could be interfaced by configuring the McASP in I2S mode and make use of the left/right frame sync as the signal to trip the conversion and then read two channels. Since the ADC is a single channel the first one would be ignored and EDMA could be used to pull out the useful channel. 

That's the strawman outline.  Hoping you can provide either further guidance here or through an app note or perhaps a reference design.

Many thanks.

  • 0
    TI__Expert 4405 points
    Hello,

    I have controlled an I2S slave using an SPI interface and we do have an AppNote that describes this, that provides some insights : www.ti.com/.../slaa449a.pdf

    Controlling an SPI slave using the I2S interface will be a little more tricky. The LRCLK with 50% duty cycle would allow data to be transferred only during the low cycle. There is also less control on the timing parameters.

    Maybe if you could give some more details we might be able to work out a better fit with the DSP.

    - You mentioned that you need to pick only the 16MSBs. What are the specs you are trying to meet with the ADC?
    - To the extent possible, if you can describe the end-application system goals you are trying to achieve or a high-level block diagram, it would help.

    Regards,
    Sandeep
  • 0 in reply to Sandeep Kasargod
    Intellectual 365 points

    Hi Sandeep:

    The system diagram is pretty simple. 4 ADS8881 ADCs connected to a DSP in a fashion that supports simultaneous sampling at 512KSPS.  For power consumption reasons, the preference is to avoid having to use an FPGA between the converters and the DSP.  The data will be DMA'ed to a suitable system memory pool, block processed, and then passed to a suitable storage element - either an SD card or more likely a SATA connected solid state drive.  Its a continuous sampling broadband acoustic data logging system with signal processing capability optimized for low power consumption and able to store very large data sets for retrieval at a later time.   One correction to the original post is that in fact all 18 bits of the converter are of interest. 

    If it isn't possible to use the McASP as the interface port, an alternative connection scheme would be acceptable provided it fell within the bounds of the system as description above - if possible.

    The choice of the converter is fixed and based primarily on the power consumption of the ADS8881, its bit depth, and its performance.   The choice of the DSP is not yet irreversible and was focused on the C6748 largely due to its hardware support for SATA and SD, its power consumption profile and it appeared to have sufficient arithmetic and data movement bandwidth to do the job. 

    The outstanding question is with regard to interfacing the DSP to the converter bank.  Hoping you can offer some guidance here.

    Many thanks.

  • 0 in reply to EngH060
    TI__Expert 4405 points
    Hello,

    Recording our off-line discussion here to close this post.

    Our analysis shows that it should be possible to connect the 4 ADS8881s to the C6748 DSP using I2S. The caveat is that the clock used by the McASP on the DSP is shared with other modules that care needs taken to ensure that end system does not impose conflicting requirements on this shared clock.

    Regards,
    Sandeep