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ADS131 START and DRDY

Todd Comins8
Prodigy 70 points

Other Parts Discussed in Thread: ADS131E04

We are using the ADS131E04. From the datasheet...

Top of page 32...

Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in
Figure 29, the DRDY output goes high when conversions are started and then goes low when data is available.
Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to
complete.
 
The text quoted above and the associated Figure 29 both lead me to believe that you will get a DRDY for the last conversion EVEN THOUGH START has been taken low to end sampling. The text below is contradictory in that regard.
 
 Bottom of page 27...
The START pin must be set high (for a minimum of 2 tCLKs) or the START command sent to begin conversions.
When START is low, or if the START command is not sent, the device does not issue a DRDY signal
(conversions are halted).
Can anyone make this clear... If START is driven low... will there still be DRDY for a conversion that was in progress when START was taken low?
Thanks!
  • 0
    TI__Mastermind 38745 points
    Hey Todd,

    Sorry for the delay. We are currently looking into this and will have an answer for you shortly.

    Regards,
    Brian Pisani
  • 0
    TI__Mastermind 38745 points
    Hey Todd,

    After reviewing the design, it looks like a final conversion will complete and a DRDY signal will be given following the START pin clearing or the STOP command being decoded. Following that, further conversions will be blocked.

    This is to say that the information on page 32 is correct and the information on page 27 is misleading. I will make sure this gets fixed in the next revision.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Prodigy 70 points

    Thanks Brian. We have been able to confirm this in the lab as well.

    FYI...

    In our test we generated a 2 clock START pulse (synchronous with ADC clock) at 2 KHz (500uS period). We had the ADC setup for 16 KHz sampling to keep the "settling time" under one START pulse period. We see DRDY transition high once START is asserted. DRDY stays high when START is released and subsequently transition low after the settling time delay.

    Todd

  • 0 in reply to Todd Comins8
    TI__Mastermind 38745 points
    Todd,

    That test sounds totally valid. I'm glad you were able to confirm this and again apologies for the delayed response.

    Regards,
    Brian Pisani