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LM98640 weird behavior

iasvc
Prodigy 30 points
Other Parts Discussed in Thread: LM98640CVAL

Hi all,

I use two LM98640 on the same board to digitize a 4-output CCD.
In a first step, I used the test patterns to validate my digital part inside FPGA.
All were fine and I checked the LVDS voltage which were good too.

In a second step, when I wanted to digitize the CCD video outputs, the behavior of the LM98640 changed:

- the LVDS voltages are not the same :
300mV low and 1.5V high (with 100Ohm terminaison resistor)
and only the low voltage changes when I change the "LVDS Amplitude and Common Mode Voltage" register

- the result of the conversion looks very noisy around a fixed mean value whatever we put on the OS- input video signal (fixed voltage from fonction generator) and whatever the values of the PGA and offset registers:
Mean value (decimal) ~10200 and the 10 LSB are flickering thus from ~9700 to 10700

Is this behavior is known ?
Is there something to do to check the health of the parts ?

Thanks a lot

vincent

  • 0
    TI__Genius 17125 points

    Hello Vincent,

    Are you using the space grade product in the ceramic package or the commercial product in the plastic package?

    Are using the part in CDS or sample and hold mode?   How is the OS+ pin connected.   Remember, if in S/H mode, OS- must never be taken higher than OS+.   If in CCD mode, OS+ should be connected to ground through a 0.1 uF cap.

    One thing I would suggest trying first is run the part with no signals on the input and adjust the fine and coarse DAC settings to see if you get an output and can move the output reading up or down by changing the DAC settings.  You should then be able to multiply the DAC setting using the PGA.

  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 30 points

    Hello Kirby!

    Yes sorry I forgot to mention that I actually use the space grade product in the ceramic package LM98640W-MPR (prototypes parts).

    I use the CDS mode to digitize an e2V CCD.
    The OS+ pin is connected to ground with a 100n capacitor and also connected to the VCLP pin which is grounded with 4.7uF + 100nF (so OS+ is grounded with 4.7uF+200nF) . But I'm not sure to well understand how to use the VCLP pin and if I need to use it.

    When you say "in S/H mode, OS- must never be taken higher than OS+" , do you mean that it is destructive ? or simply a non-sense ?

    I'll try what you suggest and come back to you.


    Thanks

  • 0 in reply to iasvc
    TI__Genius 17125 points

    VCLP can be used as a reference in S/H mode.   It isn't necessary in CDS mode.

    Remember how CDS works.   It takes two samples, during a pixel period, compares them and the output is the difference between the two samples.   If you are just putting in a low frequency sine wave, you might not be seeing a big enough difference between the samples to get a high output.   Unless you are synchronizing that wave with the capture windows, you will just see random outputs.

    In S/H mode, taking OS- higher than OS+ with result in a 0 output.   It is not imediately destructive but long term it could impact the life of the part.

    Note that we have an evaulation board available:  LM98640CVAL

     

  • 0 in reply to Kirby Kruckmeyer96848
    Prodigy 30 points
    Hi,
    Even if VCLP is not necessary in CDS mode, can it still be connected to OS+ ? I am intending of using the LM98640 in a configuration were both S/H mode and CDS can be used. For instance, I would use CDS mode at 10MHz of pixel rate while I would use S/H and do the CDS in the digital domain at 100kHz of pixel rate. S/H required the OS+ and VCLP to be tied together. I want to make sure that it will not prevent CDS mode from working. Thanks.
  • 0 in reply to Olivier Daigle
    TI__Genius 17125 points

    We do not see a problem with this approach.   In CDS mode, OS+ should be isolated enough that it will not impact the track and hold. 

    However, we have not tried or tested this configuration.   You may want to design your board so that you have some flexibility in case you see an issue.