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DAC34H84

new2day
Expert 1950 points
Other Parts Discussed in Thread: DAC34H84, LMK03806

With DAC34H84, when running in coarse mixer mode with SYNC in a single source mode and DAC PLL is disabled, we are observing the mirror signal on the spectrum.

For example, when CMIX = Fs/8 and the complex data of 6.25MHz at 100MHZ are fed to the DAC, both 56.25MHz and 43.75MHz are observed with 43.75MHz ~15dB lower than 56.25MHz.

-          The level delta between the signal and the mirror is depending on the signal frequency also the clock rate

-          The DACCLK and DAC data clock are from the same PLL(LMK03806)

 

We’ve test the DAC in the real mode as well as enabling the interpolator only without mixer, both cases, the DAC outputs look fine.

It looks like I/Q mismatching somewhere and mostly likely inside the DAC. 

  • 0
    TI__Guru* 79364 points
    Ying,

    With Fs/8 coarse mixer, the mixing mode is expecting complex quadrature data (I/Q). If the input source on channel A and B are both real signal without any quadrature realationship, then the complex mixer will not be able to suppress the sideband. Hence explains the mirror image that you are seeing.

    The only coarse mixer mode that can accept real input data are Fs/2 mode. All other modes (including fine mixer) requires complex data.

    -Kang
  • 0 in reply to Kang Hsia
    Expert 1950 points
    complex data are sent to the DAC, I to A and Q to B, for example. Thank you.
  • 0 in reply to new2day
    TI__Guru* 79364 points
    Hi Ying,

    If the suppression changes with clock frequency, perhaps it has to do with the I/Q data input latching. The Fs/8 coarse mixer is a fixed algorithm and does not require initialization. Unless the DSP path is broken (highly unlikely), I do not believe the issue is due to the coarse mixer.

    Please try to shift the input I or input Q data stream by one sample (one way or the other) to see if it fix the I/Q imbalance. Perhaps there was a data shift on the FPGA/ASIC side.

    The DAC's IO pattern test would also help verify the input timing.

    -Kang
  • 0 in reply to Kang Hsia
    Expert 1950 points
    HI Kang,

    1. I can try to shift the I/Q data. Our complex data was generated from MATLAB.
    2. please note the DAC outputs are both fine with real and only the interpolation (no mixer), nice and clean from both time and frequency domain.
    3. what did you mean no initialization.
    Thank you.
  • 0 in reply to new2day
    Expert 1950 points
    Hi Kang,

    It's OK now, turns out, the complex data from MATLAB is offset by 1 sample. Thank you.