Dear team,
we have some questions about the ADS1115-Q1 in it's internal structure.
About the setup: The ADS will be used with the maximum sampling rate (860 SPS), reading the two differential channels (AIN0-AIN1 and AIN2-AIN3) alternatively one after the other. Operation is in power-down single shot mode, because the conversion timing is controlled by the SW.
Could you give us some details about the conversion time of the device?
For example: Is it the time between the I2C ACK bit when the configuration is written (OS set to 1) and the first bit of the conversion register read-out?
It would be important that we know how long the data are present in the conversion register, in order to optimize the sequencing.
Thank you very much and best regards
Martin