DAC37J84 JESD204B SYNC Setting?

Henry,

The procedure for the DAC37J84 SYNC are the following:
1. upon powering up, the 0x4A register init_state = 2b1111 and jesd_reset = 2b0, the LVDS SYNC pair should be logic HIGH
2. program 0x24 and 0x5C accordingly to allow SYSREF pulses to be registered in the state machine.
3. program all the JESD204B and DAC parameters.
4. write 0x4A register = init_state = 2b1111, jesd_resetn = 2b1
5. write 0x4A register = init_state = 2b0000, jesd_resetn = 2b1.
6. The JESD204B block is initialized at this point, upon issuing a sysref pulse, the LVDS SYNC pair should be logic LOW, requesting CGS from JESD204B transmitter.
7. upon completion of CGS and stage to enter ILA, the SYNC should be logic High.

Please help clarify which stage the SYNC does not work.

Also, you mentioned elevating VDD from 0.9V to 0.95V will allow SYNC to work. Is this measured on the device pin after PCB trace loss and power filters? Please note that VDD draws sufficient current, and any drop in voltage due to resistance loss will cause the voltage threshold to drop below recommended value. I would advise the customer to measure the voltage during operation near the device pin as much as possible to check the actual voltage level. They may use the ATEST feature in config27 if needed to measure internal nodal voltages.

-Kang