ADC sampling rate error

Hi Benjamin,

On the ADS8406, the sampling rate is directly controlled by the user via the CONVST pin where the maximum data rate supported is 1.25MHz.   Therefore, the error in sampling rate is dependent on the jitter and errors associated with the external CONVST signal.

The device is a SAR ADC and the acquisition cycle ends at the falling edge of CONVST where the conversion period starts. The sampling of the signal occurs immediately after the falling edge of CONVST where the aperture delay is a typical of 2nS and the aperture jitter is 25ps.  You are correct that the clock driving the ADC controlling the conversion period is internal, with a conversion period minimum of 500ns to a maximum 650ns.  After the conversion (or hold) period lapses, the device returns to acquisition mode.

Please refer to Figure 1 and Figure 2 for the timing for conversion and acquisition cycles.

Let us know if you have questions,

Best Regards,

Luis