Hello,
we are using two DAC DAC5682Z in a new our product. The instrument is a sort of waveform generator. The DAC are used without interpolation, only one channel on at 1 GSPS.
We are generating the 1 GHz clock with a CDCE6005 that provide also a 125 MHz clock to the FPGA device that generate the digital stream to the DAC. The FPGA generates the data using SERDES converters. Also the clock is generated using serdes providing the sequence 1010. We checked the frequency output from the FPGA (that is 500MHz) and we also analized the data bus and everithing is ok. The FPGA used is a Kintex 7.
We are following the startup sequence as is written (exactly) on the datasheet.
Sometimes the DAC, after the initialization, start generating a signal with several spikes. To test the DAC behaviour we are generating a ramp with a counter in the FPGA. Each ns the DAC output increases by an LSB. When the spikes they are allways at the same time distance; this means that the problem involves allways one bit (not allways the same). The problem is that this appens about the 4% of the times without any regularity.
There are some strange thinks:
1) If the DAC starts in the correct way (96%) it works correctly forever (we tested for several days)
2) If the DAC starts with the spikes the spike are present "forever". We have the possibility at runtime to shift date and clock. Any phase we select between clock and data the spike never disappear on the output (we can just make they stronger).
3) checking the DLL locked bit, DLL results allways locked
4) the datasheet suggests that for a 500MHz DLCK the correct value of the register 10 (DLL phase shift) is C0. My tests indicate that good results could be achieved with 0x08.
5) with a clock of 500MHZ - 200Mhz (DCLK) the problem never happens.
Our idea is that the DLL sometime does not locked corrctly even if the lock bit is 1.
We tested almost everithing but now we need your help.
Thanks
Andrea Abba