Last month, I downloaded the JESD204B TI Reference design from TI's website and built this reference design by running a single script under Vivado 2015.1. The synthesis and implementation were succeeded, and the bitstream is generated. There are no errors and critical warnings.
Recently I upgraded the Vivado version from 2015.1 to 2015.4. I openned the same project under Vivado 2015.4, and run synthesis and impelementation. However, this time there are 2 critical warnings after the implementation is completed.
It says:"
[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
Resolution: Verify that the timing was met or had small violations at all previous steps (synthesis, placement, power_opt, and phys_opt). Run report_timing_summary and analyze individual timing paths.
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
"
I didn't modify the project which is generated by Vivado 2015.1. I just open it under Vivado 2015.4, upgraded the IPs and then run synthesis and implementation.
Now I'm confused, these are no such critical warnings under Vivado 2015.1.
Could you please tell me why these critical warnings occurred under Vivado 2015.4?
I have asked this question in Xilinx forum, they suggested me to contact with TI.
Thanks,
