Resetting Multiple (3x) ADC08D1520 to make them synchronize

Hi Reza,

Someone will get back with you shortly.

Ken.

Hello Jim and Ken,
Thank you so much for the Very helpful document regarding the multiple ADC synchronization.
I will get back to you after testing it.
Best Regards,
-Reza

Hello Jim,

I have a question regarding the part 5.0 (Reset using ADC CLK start/stop method) of the PDF file you addressed in your last post, which seems to be an easier way to synchronize multiple ADC08D1520's (3x in my case).

I have a low jitter 1.5GHz clock source and use LMK01020 (LVPECL CLK BUF from TI) as the CLK buffer to drive 3 ADCs CLK+/- inputs.

Just as FYI, LMK01020 has VOD(max)=965mV (or say 1.37VPP) and this LVPECL CLK (ac coupled) seems to be fine to drive the ADC08D1520 CLK+/- (Semi-LVDS) inputs with 0.4VPP<VOD_PP<2.0VPP requirement.

1.5GHz input source is ON all the time and MCU controls the LMK01020 and can turn it on or off by programming.

Would you think TI LMK01020 will be stable and clean as needed to get this reset done (clock source is always ON and stable during the reset)? Any comments about using LMK01020 for driving the CLK+/-? (I know LMK01010 is the LVDS version but its VOD is on the low side of the ADC08 CLK+/- VID requirement).

Thanks,

-Reza

Hi Reza

Please note the rules for using the method in part 5.0. These must be followed or the synchronization of DCLKs will not work.

Here are those items again for clarity:

1. Once the DCLK_RST signal is asserted, CLK+/- must cycle (low-then-high, or high-then-low) at least once before being disabled.
2. The CLK+/- signal, when disabled, may be held in the low or high state.
3. The CLK+/- signal must be disabled less than 30 ns if the device’s duty cycle stabilizer function is being used.
4. No narrow pulses are allowed when the CLK+/- signal is enabled again - i.e., the minimum clock pulse (Tpl/Tph) timing requirements must be met.
5. To prevent the AC coupled ADC CLK+/- inputs from de-biasing while the CLK is stopped, the AC coupling capacitors should be 100 nF or higher.

If you can come up with a way to make the LMK01020 meet these requirements this method could work. You need to make the disabling (forcing logic low or high) and re-enabling of the LMK01020 outputs be synchronized to the CLK input of the LMK01020, and to the DCLK_RST pulse and meet the 30 ns constraint of item 3 above.

Best regards,

Jim B

Hi Jim,

Regarding item no 2. of your reply above,

2- The CLK+/- signal, when disabled, may be held in the low or high state.

It seems this part is applicable IF the ADC08D1520 CLK+/- inputs are DC coupled. Is that correct?

ADC08D1520 has its own internal DC bias on CLK+/- inputs and recommends ac coupled CLK. In my design LMK01020 (LVPECL output) is ac coupled to ADC08D1520 CLK+/-.

According to LMK01020 datasheet when GOE is driven Low then ALL outputs are pulled Low. Also I will use 120nF caps to ac couple the LMK01020 LVPECL output to ADC08D1520 CLK+/- inputs to take care of no 5. in your reply which says,

5- To prevent the AC coupled ADC CLK+/- inputs from de-biasing while the CLK is stopped, the AC coupling capacitors should be 100 nF or higher

So it seems this method should work and wondering about your thoughts about my understanding described above.

Best Regards,

-Reza

Hi Reza

Regarding your follow-up questions.

2 - When stopped the ADC clock must be held in a differential 0 or 1 state. Since the inputs must be AC-coupled, this means the stopping of the clock must be very brief, so that the AC-coupling capacitors do not de-bias. 

If the LMK01020 pulls both outputs to logic low than the ADC +/- clock inputs will be set to the same voltage which is not a well defined logic level. This will not meet the requirements of this DCLK_RST method.

It sounds like you will need a different clocking circuit to meet the requirements of this DCLK_RST method.

Best regards,

Jim B

Hi Jim,

Would that work if I synchronize the 3 ADC081520 at lower speed clock (i.e. 375MHz instead of 1.5GHz) and then increase the clock to 1.5GHz?

I am thinking about using Hi-Speed glue logic (DFF/BUFF circuit suggested in the document you addressed earlier) at lower speed clock (i.e. 375MHz) and then increasing the clock to 1.5GHz to make the synchronization easier and more reliable.

Since I will use the LMK01020 CLK divider (/4) instead of synthesizer to ramp up the CLK (from 375MHz to 1.5GHz) I have a greater chance to make the CLK quality good enough for ADC08D1520 during the transition.

Best Regards,

-Reza

Hi Reza

After programming the LMK01020 the SYNC event must be used to synchronize the various dividers in the system. If the divide values are then changed while the dividers are operating, I don't think the changes will be glitchless. The divided output clocks can glitch on the transitions, which will give inconsistent numbers of clocks to each of the 3 converters. So even if they are synchronized at 375 MHz clock rate I don't think they will be synchronized once the clocks are increased to 1.5 GHz rate.

Regards,

Jim B

Hello Jim,
Regarding the question I asked you on Jan 18th
e2e.ti.com/.../1744008
and your reply, I asked about the status of LMK01020, 8x LVPECL outputs when GOE=L in Clock and Timing Forum, and below I've copied the Q&A
------------------------------------------------------------------
Q) Jan 18th, Reza A.
e2e.ti.com/.../1744146
Another question about the LMK01020 which datasheet is NOT clear about it.
According to LMK01000 page 10/26 when GOE (Global Output Enable) is driven LOW, "Clock X Output State" of all 8 outputs (which are DIFF output LVPECL in LMK01020) will be driven LOW. Is this going to be DIFFERENTIAL LOW or LOW for both +/- outputs of all 8 outputs?
------------------------------------------------------------------
A) Jan 25th,
It will be differential low.

73,
Timothy
-------------------------------------------------------------------
So , it seems I can use the easier method to synchronize the 3 ADC08D1520's by
1- Setting the DCLK_RST to HI when ADC's CLK+/- is already applied
2- Stopping the CLK+/- by using the LMK01020 GOE=LOW which will hold the CLK+/- at DIFF LOW (C=120nF to ADC's) according to Timothy answer above.
3- Bringing the DCLK_RST to LOW in less than 30ns and applying the CLK+/- by using LMK01020 GOE=HI
PS: CLK+/- stop period should be less than 30ns

Please let me know your comments.
Thanks,
-Reza

Hello Jim,
Just another question about ADC08D1520 please.
In my design I do use 3 ADC08D1520 clocked at 1.5GHz (Synthesizer making the CLK and LMK01020 used to fan it out). I am going to use 2 different methods to make them in SYNC.
But as the worst case scenario I would like to know when 3 ADC's are clocked at 1.5GHz (T=666.66 ps), does that mean their sampling time stamps could be off by less than one period which is 666.66 ps or based on the pipeline architecture of the ADC08D1520, 3 ADC's could be off more than 666.66ps?
Thanks,
-Reza

Hello Jim,

I have 3 questions and wondering if you can help me to find out the answers

1- As the worst-case scenario how much sampling between 3 ADC08D1520 will be off if the are NOT synchronized.

I am using 1.5GHz CLK+/- generated by Synthesizer and buffered using LMK01020. My understanding is that if 3 ADC0d1520 are not in sync then their sampling could be off by less than 1/1.5GHz=666.66 ps. Is that correct?

3- What's the best way to find out 3 ADC's are in sync? Using the Test Patterns generated by ADC08D1520 or ...?

2- Also for a single ADC081520 what happens if I do NOT reset it by meeting the DCLK_RST timing requirements or in other words I keep the DCLK_RST lines in unasserted state. I am using extended control mode and write the programs and use SPI interface to configure the ADC as needed.

Thanks,

-Reza

Hi Neeraj,

Thanks for your answers.

1- I am using the DCLK of each ADC for reading its digitized data, so no problem regarding the Tod difference between the ADCs.

I am driving the ADCs with low jitter, fully synchronized clocks, applied at the same time to all ADCs, and looking for post processing the digitized data by different ADCs, in case synchronization fails and ADCs are NOT in sync. This means I am looking for a work around to find out the offset between the digitized samples of different ADCs which are not in Sync.

Question 1) If I use DCLK of each ADC to read its digitized data what would be the maximum time difference between multiple ADCs based on what I mentioned above? +/- 1 ADC clock or more?

2- I understand by probing the DCLKs of different ADCs I can find out whether they are in Phase or not, but I am looking for a method in the final product to apply it after system power-up to make sure my synchronization circuit has worked properly and all 3 ADCs are in Sync.If not I need to find out the offset between the digitized data of the ADCs.

That's the reason I want to use the test pattern available in this ADC.

According to ADC08D1520 page 43/59, copied below it seems by applying the DCLK_RST of multiple ADCs at the same time (taking care of the tHR, tSR) Test Patterns of different ADCs should be in SYNC:

ADC08D1520 page 43/59: To ensure that the test pattern starts synchronously in each port, set DCLK_RST while writing the Test Pattern Output bit in the Extended Configuration Register. The pattern appears at the data output ports when DCLK_RST is cleared low.

Question 2) Would you agree with this?

Best Regards,

-Reza