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ADC12D1800RFRB FPGA time order

Hi,

I am trying to figure out the time order of the of ADC output from IDDR. I attempted to get the order from this section of the comment in the acd12d10000_rfrf.v file. 

/* The time order for des mode (above) is: (example for 8 bit adc)
* dqd1_reg[7:0] did1_reg[7:0] dq1_reg[7:0] di1_reg[7:0]
* dqd1_reg[15:8] did1_reg[15:8] dq1_reg[15:8] di1_reg[15:8]
* dqd1_reg[23:16] did1_reg[23:16] dq1_reg[23:16] di1_reg[23:16]
* dqd1_reg[31:24] did1_reg[31:24] dq1_reg[31:24] di1_reg[31:24]
*
*/

Here is what I got, {dqd_r, did_r, dq_r, di_r, dqd_f,did_f, dq_f, di_f}. But further test show this is not the right time order.Could you help me figure out the right order.

Thank you very much,

  • Hi Ethan

    I'll look into this and should have a response for you by sometime tomorrow.

    Best regards,

    Jim B

  • Thank you very much.  I have tried many ways but failed to figure out the right order so far.

    Best,

    Ethan

  • Hi Ethan

    I haven't located the information that will help me provide the direct answer to your question.

    I would suggest you try two different test signals to help figure this out. If you have a signal source and balun board that can handle low input frequencies, apply a 15 MHz input signal to the VINI input when the device is operating in DESI mode. Since this input signal is at very low frequency with respect to the sample rate it should enable you to figure out the order more easily than a high frequency signal.

    If that source cannot be used, enable the Test Pattern Mode of the ADC. In this mode the data will repeat according to the following pattern, which repeats every 5 words on each port, or every 20 samples once the data is interleaved into a single stream.

    If neither of these methods help please let me know.

    Regards,

    Jim B

  • Thank you very much. I will try your method.