We have a board design with 7 daisy chained 7760s (running in 4-20ma mode but that is not important for this discussion). We have multiple other SPI devices on same SPI bus with the 7760s. We seem to have a condition where when we have raised the LATCH pin and then do SPI traffic to a different SPI device, the 7760 takes over the SDO line and corrupts our other SPI device's sending data back to the SPI master. It's as if the 7760 is stuck in read mode. We have two different test boards and one exhibits this behavior far less than the other. My question is: how do we keep the 7760 from entering its read mode and taking over the SDO line when we are not even talking to it. When we look at the timing diagrams, it looks like once the 7760 is convinced its in read mode, it will take over the SDO line regardless of the state of the LATCH line (i.e., very contrary to how most SPI devices act in that when their CS lines are high, they stay off the bus). We have looked at the LATCH line when we are not talking to the 7760 and it seems to stay high, as expected and only transitions to low when we start talking to the devices. Our basic logic in talking to the devices is this:
Read or write command:
LATCH=0
send 21 bytes for write or read
LATCH=1
if read:
LATCH=0
send 21 bytes to read
LATCH = 1
Does this seem like the correct logic (it is what we do for all other SPI devices). The 7760s seems to correctly respond to commands we give to them (i.e., the control and data registers return correct values when we read them back). The issues is ALWAYS when we have LATCH high and we are talking to other SPI devices. As a work-around, we see that if, after a write command, we send 21 zeroes (i.e., NOP commands), this seems to kick the 7760 out of read mode. Why is it getting in read mode in the first place on a write command?
We are running at 250kHz and the times between LATCH transitions are on the order of many microseconds (all done in user-space code calling kernel space code so there are many hundreds of instructions between each LATCH transition).
Perhaps we have the DACs configured incorrectly. There seems to be very little documentation on how to configure them for DCEN mode. For my init code, I am having to write 21 bytes (3x7) seven times to get each device in turn into DCEN mode. Does this make sense?
We could really use some help in figuring out how to get the 7760 to behave properly in the daisy-chain mode.
Thanks for your consideration.
