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ADS1274 SCLK, D-flipflop, inverting buffer

Horst Bechtold
Prodigy 180 points
Other Parts Discussed in Thread: ADS1274, ADS1278, OMAP-L138

Hello,
I would like to use the ADS1274 and connect it to an OMAP-L138 for my measurement PCB and have one question regarding the inverter gate "U1" in figure 88 of the ADS1274 data sheet.

I want to operate the ADC in Frame-Sync output format at the highest possible samping rate, so CLK should be something about 36 MHz, and SPI is not an option.

As far as I understand the interface circuit, the D-flipflop "U2" should 're-synchronize' the data stream, so that the timing of the data bit at the uP-Port DR matches the bit clock SCLK, regardless of some (minor) phase shift on its way across the board.

BUT: for my understanding, the inverter makes things worse than better, because the '74 D-flipflop is positive-edge triggered and the ADS1274 delivers the next data bit after the falling edge of the SCLK signal, feed to the input of the inverter. So the data bit should be stable at the time when the **rising** edge of SCLK arrives, not at its falling edge. But the inverter transforms the falling edge of SCLK to an rising edge, so that the flipflop captures the ADS1274 output data bit just in that moment, when it changes its state (or a few nanoseconds later).

I do believe, that the circuit works and is well designed, but can somebody be so kind to explain, what the inverter is for, or where my missunderstanding is?

Thank you in advance, Horst

  • 0
    TI__Guru 62286 points

    Hello Horst,

    Thanks for your question.

    The important thing to keep in mind is that, on the SCLK falling edge, DOUT does not change immediately. In fact, there is a minimum 10ns delay called tDOHD. So, when the D flip-flop sees a rising clock edge (corresponding to the SCLK falling edge), the status of D will still hold the previous value long enough to output that value on Q before the DOUT bit transitions.

    Below, I've drawn an example of why re-clocking the data is necessary for a 31ns tMSBPD. Here, the frame-sync pulse width is equal to the SCLK period of 27ns. In your DSP, you should be able to set a 1-SCLK delay such that the MSB is latched on the second SCLK rising edge instead of the first one.

    The actual propagation delay that you will observe from the ADS1278 will depend on your DVDD supply. For example, if DVDD is between 2V and 2.2V, the max tMSBPD will be 21ns, so you will only need to use this technique for SCLK speeds faster than 1/21ns = 47.6MHz

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 180 points

    Hello Ryan,

    thank you very much for this explanation.

    What I overlooked on my first glance onto the data sheets and circuit diagrams of the ADS1278-PDK, including MMB0, was the fact, that one bit clock period of the data stream matches just about the tMSBPD delay time from frame sync to the first data bit at the highest frame rate and full speed SCLK frequency.

    If one has a lot of channels to convert using daisy-chaining, the bit clock rate SCLK matters, because the whole number of bits per frame ist limited to 256 at maximum bit clock rate. In our case, the situation looks a bit easier. We need only four channels, so one '1274 connected to the OMAP-L138 will fit.

    But we want to use the High-Res mode with 27MHz SCLK also, sw-configurable. In that case, tMSBPD is a bit less than on SCLK period time at full SCLK-speed and the flipflop will latch the 2nd data bit, instead of the MSBit. So my doubts regarding the flipflop clocking remain.

    Should'nt it be better to work with SCLK = 1/2 CLK frequency? Four channels, corresponding 96 data bits, will still fit into the then128 bit long frame, and it should be possible to use SCLK as the OMAP's receive bit clock CLKR for both ADS1274 modes (High-Speed and High-Res).

    If I understand some remarks in the McBSP0 timing data (OMAP data sheet SPRS586I, pg. 161 .. 168), then the CLKR output polarity can be changed by module config settings, so I can decide by software, which edge of the SCLK, conncted directly to CLKR, latches the data bit stream into the OMAPs receive register. (I still failed to read most of the 1800 pages of the OMAP's Technical Reference Manual ;-)

    Another point is, that we need a high resolution control of the sample timing and need to timely match each data sample's time stamp with a couple of external events, we intend to capture within the OMAP's eCAP module. So we will implement a separate clock generation / management block with a low phase noise XO and static frequency dividers (no PLL) and derive the sampling / modulator clock CLK and the eCAP counting clock from that, hoping that the OMAP is able to generate SCLK (=CLCR) and FSYNC (=FSR) in a stable phase relationship to that.

    Do you think that this is reasonable approach and reliable?

    Meanwhile I found this post: https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/98323 , which explaines the same question from another point of view.

    Best regards, Horst

  • 0 in reply to Horst Bechtold
    TI__Guru 62286 points

    Hello Horst,

    Horst Bechtold said:
    But we want to use the High-Res mode with 27MHz SCLK also, sw-configurable. In that case, tMSBPD is a bit less than on SCLK period time at full SCLK-speed and the flipflop will latch the 2nd data bit, instead of the MSBit. So my doubts regarding the flipflop clocking remain.

    I looked at this a little more closely and you will not lose any data in the condition where the propagation delay (either tMSBPD or tDOPD) is less than the SCLK period (tSCLK). As you can see in the figure below, the MSB does not change immediately (tDOHD), so the flip-flop will latch the MSB and hold it on Q until the next /SCLK rising edge. Alternatively, you could set your DSP to read on the SCLK falling edge, if that's possible. Then I suppose you wouldn't need this technique at all.

    I think I need to take back what I said in my last post when I said, "you will only need to use this technique for SCLK speeds faster than 1/[tMSBPD] (in other words, when tSCLK < tMSBPD, tDOPD). In fact, you will miss data if tSCLK < tMSBPD, tDOPD, regardless of whether or not you reclock the data with the flip-flop (see figure below). The solution here would be to slow down your SCLK (increasing tSCLK) or change your DVDD voltage to lower the max propagation delay.

    I hope this makes sense. If you'd like me to double-check whether you need this in your system, please confirm your CLK frequency, SCLK frequency, and DVDD voltage.

    Horst Bechtold said:
    Should'nt it be better to work with SCLK = 1/2 CLK frequency? Four channels, corresponding 96 data bits, will still fit into the then128 bit long frame, and it should be possible to use SCLK as the OMAP's receive bit clock CLKR for both ADS1274 modes (High-Speed and High-Res).

    From a performance standpoint, yes, it would be optimal to use SCLK/CLK ratios of 1 / 2^n, as long as you are able to read all of the data in each frame.

    Best Regards,