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ADC12J4000EVM

Michael Robertson52
Prodigy 180 points

Other Parts Discussed in Thread: ADC12J4000

I've started using the ADC and corresponding FPGA card, I keep getting a signal which is around 1GHz and 2GHz, I'm guessing that has to do with the sampling freq, not sure whether it is within specification as I couldn't find any tolerances.

Also I read the lowest sampling freq can be 1G, Although I seem to get an error if I reduce it below about 1.9G??

  • 0
    TI__Mastermind 44680 points

    Hi Michael

    The ADC12J4000 is a 4-way interleaved ADC architecture. The 4 internal ADC cores are self-calibrated to optimize linearity and match full scale range and offset. Small residual mismatch in offset will result in low-level fixed frequency spurs at Fs/4 and Fs/2. These are probably what you are seeing. If the level is consistently above -60dBFS then there may be some other cause that requires further investigation.l

    The EVM will operate down to 1000 MHz clock rate, but I have seen some capture issues in the past. Can you try keeping the ADC EVM settings as-is for 1000 MSPS, but change the HSDC Pro setting for ADC Output Sample Rate to 1600 MSPS instead of 1000 MSPS? That different setting may allow the capture to work because it changes some of the firmware coefficients in the capture board. Let me know if this enables capture.

    Best regards,

    Jim B