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ADS54j66EVM external clock

Brian Sun
Prodigy 210 points
Other Parts Discussed in Thread: LMK04828, ADS54J66EVM

Hey guys,

    I'm trying to use the ADS54j66EVM with the onboard LMK04828 Clock Chip in the Clock distribution mode as described in section 5.1.2 of the ADS5XJ6X Evaluation Module User guide. I've removed the JP2 jumper and inserted a 122.88MHz clock signal into CLKIN(J12) of the board and loaded the LMK_Config_External_Clock Configuration file in the ADs54Jxx GUI to test if the PLL2 can be locked in the same way with the external clock. However, when I do this PLL2 does not lock. I am curious on how the external LMK04828 Clock Distribution mode is used and whether or not the external clock(fed into J12) replaces the on board vcxo which can be stepped up using the PLLs in the same manner as using the on board vcxo?

Thanks in advance for the help,

Brian

  • 0
    TI__Guru* 91947 points

    Brian,

    What is mentioned in the User's Guide is clock buffer mode, which does not use the internal VCO at all. To do what you are trying, you would have to route the signal on J12 to the OSC input of the LMK. You can do this by installing a 0 Ohm resistor at R61, 0.1uF cap at C92, a 0.1uF cap at R77 and a 0 Ohm resistor at C82, and remove C169, R62 and C121. This will provide a cap to GND on OSCINn and an AC coupled single-ended input to OSCINp. Check the LMK04828 data sheet for amplitude specifications for this input. You then should be able to get PLL2 to lock.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 210 points
    Man that does not sound fun... does the clock buffer mode just clean up the clock signal via the LMK04828? if so, how does feeding a signal into the J12 SMA change the adc sampling frequency?
  • 0 in reply to Brian Sun
    TI__Guru* 91947 points

    Brian,

    Clock buffer mode uses the clock you input and allows you use it as is or divided it down for all of the outputs. The phase noise is almost directly related to your input clock source. The device does not clean up your source, only adds very low amount of noise.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 210 points
    Jim,

    Thank you, just to clarify and confirm I'm on the right page... using the buffer mode means that both plls are bypassed the outputs are divisions set by the clock outputs tab of the LMK04828 tab in the ADS54Jxx Gui correct? For example if I input a 1GHz signal into the J12 SMA and set the clock divider on CLKout 0 and 1 to be 2 I get a 500MSPS sampling rate?

    Thanks again Jim,
    Brian
  • 0 in reply to Brian Sun
    TI__Guru* 91947 points

    Brian,

    That is correct. The only thing special is when you do a divide by 1. Then you must set the DCLK Source as shown below.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 210 points
    Jim,
    The picture didn't seem to make it through. But I don't think I will be dividing by 1. Thanks Jim! This is great news. I appreciate everything you've done for me.

    Brian
  • 0 in reply to Brian Sun
    Prodigy 210 points

    Jim, 

       I've ran into a slight wall when attempting to do this. I've fed in a 1044 MHz signal into the J12 SMA and loaded the LMK_External_Clock config and I can't seem to get the board to capture. I believe it is because the board is not providing a clock to the TSW14j56EVM board. any thoughts? 

    Thanks,

    Brian