• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 47 subscribers
  • Views 419 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8318 minimum acquisition time of 600 ns for 16 bits, 50MHz max serial clock

Susan Beiter
Prodigy 30 points

Other Parts Discussed in Thread: ADS8318

I am looking at using the ADS8318 in CS mode, 3 wire without busy indicator.  The rev A spec SLA568A gives a minimum acquisition time of 600ns, but for 16 bit data clocked on a 50MHz max SPI clock, the data acquisition should be 320ns (16 * 20ns) plus the tEN output enable time of 15ns, or 335ns.  Why does the spec say 600ns, almost twice as long?  I feel like I am missing some extra delay parameter, but there's nothing of the right order of magnitude in the table, and nothing shown in the timing figure 46 to explain a missing 265ns.  Please help - thanks!

  • 0
    TI__Genius 9335 points
    Hello Susan,

    The 600ns time is the time when ADC is acquiring the input i.e. IN+/- pins are connected to the internal sampling capacitors.
    Since the device can operate at max 500ksps, total time available between two data samples is 2us.

    Out of these 2 us, 1400ns are needed for conversion. Hence user needs to give minimum 600ns for the analog input acquisition to satisfy 500ksps max requirement.

    When the device is in this 600nsec acquisition phase, user can acquire the converted data using SCLK max of 50MHz.

    As you have correctly pointed out that your acquisition will be over after 335ns. The SDO will get into tristate mode after the 16th falling edge of SCLK. Remaining SCLK transitions will be ignored until the CONVST is pulled high.

    You can reduce the SCLK frequency till you can get 16 SCLK's in the 600ns time.

    Thanks & Regards,
    Shridhar.