Hello,
I have 3 questions and wondering if you can help me to find out the answers
1- I am musing 3 ADC08D1520 in my design and would need to know as the worst-case scenario how much sampling between 3 ADC's will be off if they are NOT synchronized. I am using 1.5GHz CLK+/- generated by Synthesizer and buffered using LMK01020. My understanding is that if 3 ADC0d1520 are not in sync then their sampling could be off by less than 1/1.5GHz=666.66 ps. Is that correct?
2- What's the best way to find out 3 ADC's are in sync? Using the Test Patterns generated by ADC08D1520 or ...?
3- Also for a single ADC081520 what happens if I do NOT reset it by meeting the DCLK_RST timing requirements or in other words if I keep the DCLK_RST lines in unasserted state. I am using extended control mode and write the programs and use SPI interface to configure the ADC as needed.
Thanks,
-Reza
