• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 465 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

adc07d1520: D_CLK_RST interface

er ober
Prodigy 70 points

Hello,

We're designing  an acquisition system using this TI ADC. We are planning on running the D_CLK_RST signal in differential mode.


I'm looking at the timing diagrams, Figure 8/,9 in the ADC datasheet, which describe this interface. Is only the falling edge of D_CLK_RST+ of importance? I ask this question, since the timing diagram suggests the rising edge should be directly inline with a falling edge of the sampling clock (which is not accessible in the FPGA).

Thank you,

Eric

  • 0
    TI__Mastermind 20541 points
    Hi,

    I am looking into this will respond as soon as I can.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    TI__Mastermind 20541 points

    Hi,

    if you read description on page 37 of the datasheet under section 1.5 MULUTIPLE ADC SYNCHRONIZATION. It mention "The DCLK_RST pulse must be of a minimum width and its deassertion(falling) edge must observe setup and hold times with respect to the rising edge of the input clock. These timing specification are listed as tpwr,trs and trh in converter electrical characteristics". The falling edge is used to make sure we meet tpwr parameter requirements.

    Regards,
    Neeraj Gill