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ADC08B3000 capture buffer size

Steven Kinkead
Prodigy 30 points
Other Parts Discussed in Thread: ADC08B3000

I’m having an issue with the 3GSPS ADC (ADC08B3000).   I am dynamically changing the ADC’s capture buffer depth from 1K to 4K using the SPI bus.   While writing to the capture buffer (WEN = ‘1’),  I am monitor the Full Flag (FF) pin.   When the capture buffer is set to 1K depth,  the Full Flag is asserted 1K samples after WEN is asserted, which is correct.  However, when the capture buffer is set to 4K depth, the Full Flag is asserted after only 3750 samples, not 4K samples. 

Also, when I read the sampled data from the capture buffer, It appears to be skewed in time, so I believe the buffer is not collecting the full 4K samples.  Do you know what could cause this? 

  • 0
    TI__Mastermind 44560 points

    Hi Steven

    After you change the capture buffer size setting and before initiating data writes, are you resetting the buffer pointers by asserting the RESET input?

    Are you setting the ASW (Auto Stop Write) bit to prevent over-writing the earlier samples in the buffer when it is full?

    If you are following the timing as shown in Figure 15 of the datasheet I expect you should achieve the full capture depth of 4096 samples.

    Please send the sequence of register configuration settings you are writing during device initialization and the settings written when changing from 1k to 4k and 4k to 1k.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 30 points
    I am not asserting RESET after changing the capture buffer size. I'll give that a try and report back.
  • 0 in reply to Steven Kinkead
    Prodigy 30 points
    In Figure 15, I do not see the specifications for the timing parameters tPWRST and tDWEN listed anywhere in the document.
  • 0 in reply to Steven Kinkead
    TI__Mastermind 44560 points

    Hi Steven

    I haven't been able to find definitive information on either of those two parameters, but did get some guidance from the original designer of that product.

    For tPWRST, I would allow a minimum asserted time of 3 Write Clock periods (6 ADC input clock periods). Having a longer RESET high time is fine.

    For tDWEN it is probably on the order of 2 Write Clock periods, plus some amount of logic gate delay. You can confirm what you see by probing the RESET and WEN signals once you get RESET active.

    Sorry I can't provide more solid answers but this will be enough to meet the requirements of the chip.

    Best regards,

    Jim B